arch/x86/kernel/amd_nb.c

292

struct pci_dev *F4;

arch/x86/kernel/amd_nb.c

301

F4 = node_to_amd_nb(0)->link;

arch/x86/kernel/amd_nb.c

302

if (!F4)

arch/x86/kernel/amd_nb.c

305

if (pci_read_config_dword(F4, 0x164, &val))

crypto/rmd160.c

118

ROUND(cc, dd, ee, aa, bb, F4, K4, in[1], 11);

crypto/rmd160.c

119

ROUND(bb, cc, dd, ee, aa, F4, K4, in[9], 12);

crypto/rmd160.c

120

ROUND(aa, bb, cc, dd, ee, F4, K4, in[11], 14);

crypto/rmd160.c

121

ROUND(ee, aa, bb, cc, dd, F4, K4, in[10], 15);

crypto/rmd160.c

122

ROUND(dd, ee, aa, bb, cc, F4, K4, in[0], 14);

crypto/rmd160.c

123

ROUND(cc, dd, ee, aa, bb, F4, K4, in[8], 15);

crypto/rmd160.c

124

ROUND(bb, cc, dd, ee, aa, F4, K4, in[12], 9);

crypto/rmd160.c

125

ROUND(aa, bb, cc, dd, ee, F4, K4, in[4], 8);

crypto/rmd160.c

126

ROUND(ee, aa, bb, cc, dd, F4, K4, in[13], 9);

crypto/rmd160.c

127

ROUND(dd, ee, aa, bb, cc, F4, K4, in[3], 14);

crypto/rmd160.c

128

ROUND(cc, dd, ee, aa, bb, F4, K4, in[7], 5);

crypto/rmd160.c

129

ROUND(bb, cc, dd, ee, aa, F4, K4, in[15], 6);

crypto/rmd160.c

130

ROUND(aa, bb, cc, dd, ee, F4, K4, in[14], 8);

crypto/rmd160.c

131

ROUND(ee, aa, bb, cc, dd, F4, K4, in[5], 6);

crypto/rmd160.c

132

ROUND(dd, ee, aa, bb, cc, F4, K4, in[6], 5);

crypto/rmd160.c

133

ROUND(cc, dd, ee, aa, bb, F4, K4, in[2], 12);

crypto/rmd160.c

172

ROUND(eee, aaa, bbb, ccc, ddd, F4, KK2, in[6], 9);

crypto/rmd160.c

173

ROUND(ddd, eee, aaa, bbb, ccc, F4, KK2, in[11], 13);

crypto/rmd160.c

174

ROUND(ccc, ddd, eee, aaa, bbb, F4, KK2, in[3], 15);

crypto/rmd160.c

175

ROUND(bbb, ccc, ddd, eee, aaa, F4, KK2, in[7], 7);

crypto/rmd160.c

176

ROUND(aaa, bbb, ccc, ddd, eee, F4, KK2, in[0], 12);

crypto/rmd160.c

177

ROUND(eee, aaa, bbb, ccc, ddd, F4, KK2, in[13], 8);

crypto/rmd160.c

178

ROUND(ddd, eee, aaa, bbb, ccc, F4, KK2, in[5], 9);

crypto/rmd160.c

179

ROUND(ccc, ddd, eee, aaa, bbb, F4, KK2, in[10], 11);

crypto/rmd160.c

180

ROUND(bbb, ccc, ddd, eee, aaa, F4, KK2, in[14], 7);

crypto/rmd160.c

181

ROUND(aaa, bbb, ccc, ddd, eee, F4, KK2, in[15], 7);

crypto/rmd160.c

182

ROUND(eee, aaa, bbb, ccc, ddd, F4, KK2, in[8], 12);

crypto/rmd160.c

183

ROUND(ddd, eee, aaa, bbb, ccc, F4, KK2, in[12], 7);

crypto/rmd160.c

184

ROUND(ccc, ddd, eee, aaa, bbb, F4, KK2, in[4], 6);

crypto/rmd160.c

185

ROUND(bbb, ccc, ddd, eee, aaa, F4, KK2, in[9], 15);

crypto/rmd160.c

186

ROUND(aaa, bbb, ccc, ddd, eee, F4, KK2, in[1], 13);

crypto/rmd160.c

187

ROUND(eee, aaa, bbb, ccc, ddd, F4, KK2, in[2], 11);

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

2022

ASPEED_PINCTRL_PIN(F4),

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

656

SIG_EXPR_LIST_DECL_SINGLE(F4, SDA6, I2C6, I2C6_DESC);

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

657

PIN_DECL_1(F4, GPIOK3, SDA6);

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

659

FUNC_GROUP_DECL(I2C6, C1, F4);

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1315

SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1316

SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0);

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1317

PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0));

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1318

FUNC_GROUP_DECL(ADC0, F4);

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

2020

ASPEED_PINCTRL_PIN(F4),

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

2564

ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4),

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

2565

ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4),

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1439

SIG_EXPR_LIST_DECL_SESG(F4, RGMII2RXD1, RGMII2, SIG_DESC_SET(SCU400, 21),

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1441

SIG_EXPR_LIST_DECL_SESG(F4, RMII2RXD1, RMII2, SIG_DESC_SET(SCU400, 21),

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1443

PIN_DECL_2(F4, GPIO18C5, RGMII2RXD1, RMII2RXD1);

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1459

FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1);

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1460

FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1);

drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c

1843

ASPEED_PINCTRL_PIN(F4),

drivers/pinctrl/pinctrl-pic32.c

1409

PIC32_PINCTRL_GROUP(84, F4,

drivers/ras/amd/atl/access.c

109

err = pci_write_config_dword(F4, ficaa_addr, ficaa);

drivers/ras/amd/atl/access.c

115

err = pci_read_config_dword(F4, ficad_addr, lo);

drivers/ras/amd/atl/access.c

68

struct pci_dev *F4;

drivers/ras/amd/atl/access.c

78

F4 = node_to_amd_nb(node)->link;

drivers/ras/amd/atl/access.c

79

if (!F4) {

lib/crypto/md5.c

100

MD5STEP(F4, d, a, b, c, in[7] + 0x432aff97, 10);

lib/crypto/md5.c

101

MD5STEP(F4, c, d, a, b, in[14] + 0xab9423a7, 15);

lib/crypto/md5.c

102

MD5STEP(F4, b, c, d, a, in[5] + 0xfc93a039, 21);

lib/crypto/md5.c

103

MD5STEP(F4, a, b, c, d, in[12] + 0x655b59c3, 6);

lib/crypto/md5.c

104

MD5STEP(F4, d, a, b, c, in[3] + 0x8f0ccc92, 10);

lib/crypto/md5.c

105

MD5STEP(F4, c, d, a, b, in[10] + 0xffeff47d, 15);

lib/crypto/md5.c

106

MD5STEP(F4, b, c, d, a, in[1] + 0x85845dd1, 21);

lib/crypto/md5.c

107

MD5STEP(F4, a, b, c, d, in[8] + 0x6fa87e4f, 6);

lib/crypto/md5.c

108

MD5STEP(F4, d, a, b, c, in[15] + 0xfe2ce6e0, 10);

lib/crypto/md5.c

109

MD5STEP(F4, c, d, a, b, in[6] + 0xa3014314, 15);

lib/crypto/md5.c

110

MD5STEP(F4, b, c, d, a, in[13] + 0x4e0811a1, 21);

lib/crypto/md5.c

111

MD5STEP(F4, a, b, c, d, in[4] + 0xf7537e82, 6);

lib/crypto/md5.c

112

MD5STEP(F4, d, a, b, c, in[11] + 0xbd3af235, 10);

lib/crypto/md5.c

113

MD5STEP(F4, c, d, a, b, in[2] + 0x2ad7d2bb, 15);

lib/crypto/md5.c

114

MD5STEP(F4, b, c, d, a, in[9] + 0xeb86d391, 21);

lib/crypto/md5.c

99

MD5STEP(F4, a, b, c, d, in[0] + 0xf4292244, 6);