arch/sparc/net/bpf_jit_comp_32.c

71

(F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))

arch/sparc/net/bpf_jit_comp_32.c

73

#define ADD F3(2, 0x00)

arch/sparc/net/bpf_jit_comp_32.c

74

#define AND F3(2, 0x01)

arch/sparc/net/bpf_jit_comp_32.c

75

#define ANDCC F3(2, 0x11)

arch/sparc/net/bpf_jit_comp_32.c

76

#define OR F3(2, 0x02)

arch/sparc/net/bpf_jit_comp_32.c

77

#define XOR F3(2, 0x03)

arch/sparc/net/bpf_jit_comp_32.c

78

#define SUB F3(2, 0x04)

arch/sparc/net/bpf_jit_comp_32.c

79

#define SUBCC F3(2, 0x14)

arch/sparc/net/bpf_jit_comp_32.c

80

#define MUL F3(2, 0x0a) /* umul */

arch/sparc/net/bpf_jit_comp_32.c

81

#define DIV F3(2, 0x0e) /* udiv */

arch/sparc/net/bpf_jit_comp_32.c

82

#define SLL F3(2, 0x25)

arch/sparc/net/bpf_jit_comp_32.c

83

#define SRL F3(2, 0x26)

arch/sparc/net/bpf_jit_comp_32.c

84

#define JMPL F3(2, 0x38)

arch/sparc/net/bpf_jit_comp_32.c

87

#define RD_Y F3(2, 0x28)

arch/sparc/net/bpf_jit_comp_32.c

88

#define WR_Y F3(2, 0x30)

arch/sparc/net/bpf_jit_comp_32.c

90

#define LD32 F3(3, 0x00)

arch/sparc/net/bpf_jit_comp_32.c

91

#define LD8 F3(3, 0x01)

arch/sparc/net/bpf_jit_comp_32.c

92

#define LD16 F3(3, 0x02)

arch/sparc/net/bpf_jit_comp_32.c

93

#define LD64 F3(3, 0x0b)

arch/sparc/net/bpf_jit_comp_32.c

94

#define ST32 F3(3, 0x04)

arch/sparc/net/bpf_jit_comp_64.c

139

(F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))

arch/sparc/net/bpf_jit_comp_64.c

141

#define ADD F3(2, 0x00)

arch/sparc/net/bpf_jit_comp_64.c

142

#define AND F3(2, 0x01)

arch/sparc/net/bpf_jit_comp_64.c

143

#define ANDCC F3(2, 0x11)

arch/sparc/net/bpf_jit_comp_64.c

144

#define OR F3(2, 0x02)

arch/sparc/net/bpf_jit_comp_64.c

145

#define XOR F3(2, 0x03)

arch/sparc/net/bpf_jit_comp_64.c

146

#define SUB F3(2, 0x04)

arch/sparc/net/bpf_jit_comp_64.c

147

#define SUBCC F3(2, 0x14)

arch/sparc/net/bpf_jit_comp_64.c

148

#define MUL F3(2, 0x0a)

arch/sparc/net/bpf_jit_comp_64.c

149

#define MULX F3(2, 0x09)

arch/sparc/net/bpf_jit_comp_64.c

150

#define UDIVX F3(2, 0x0d)

arch/sparc/net/bpf_jit_comp_64.c

151

#define DIV F3(2, 0x0e)

arch/sparc/net/bpf_jit_comp_64.c

152

#define SLL F3(2, 0x25)

arch/sparc/net/bpf_jit_comp_64.c

153

#define SLLX (F3(2, 0x25)|(1<<12))

arch/sparc/net/bpf_jit_comp_64.c

154

#define SRA F3(2, 0x27)

arch/sparc/net/bpf_jit_comp_64.c

155

#define SRAX (F3(2, 0x27)|(1<<12))

arch/sparc/net/bpf_jit_comp_64.c

156

#define SRL F3(2, 0x26)

arch/sparc/net/bpf_jit_comp_64.c

157

#define SRLX (F3(2, 0x26)|(1<<12))

arch/sparc/net/bpf_jit_comp_64.c

158

#define JMPL F3(2, 0x38)

arch/sparc/net/bpf_jit_comp_64.c

159

#define SAVE F3(2, 0x3c)

arch/sparc/net/bpf_jit_comp_64.c

160

#define RESTORE F3(2, 0x3d)

arch/sparc/net/bpf_jit_comp_64.c

163

#define RD_Y F3(2, 0x28)

arch/sparc/net/bpf_jit_comp_64.c

164

#define WR_Y F3(2, 0x30)

arch/sparc/net/bpf_jit_comp_64.c

166

#define LD32 F3(3, 0x00)

arch/sparc/net/bpf_jit_comp_64.c

167

#define LD8 F3(3, 0x01)

arch/sparc/net/bpf_jit_comp_64.c

168

#define LD16 F3(3, 0x02)

arch/sparc/net/bpf_jit_comp_64.c

169

#define LD64 F3(3, 0x0b)

arch/sparc/net/bpf_jit_comp_64.c

170

#define LD64A F3(3, 0x1b)

arch/sparc/net/bpf_jit_comp_64.c

171

#define ST8 F3(3, 0x05)

arch/sparc/net/bpf_jit_comp_64.c

172

#define ST16 F3(3, 0x06)

arch/sparc/net/bpf_jit_comp_64.c

173

#define ST32 F3(3, 0x04)

arch/sparc/net/bpf_jit_comp_64.c

174

#define ST64 F3(3, 0x0e)

arch/sparc/net/bpf_jit_comp_64.c

176

#define CAS F3(3, 0x3c)

arch/sparc/net/bpf_jit_comp_64.c

177

#define CASX F3(3, 0x3e)

arch/x86/kernel/cpu/mce/inject.c

442

struct pci_dev *F3;

arch/x86/kernel/cpu/mce/inject.c

450

F3 = nb->misc;

arch/x86/kernel/cpu/mce/inject.c

451

if (!F3)

arch/x86/kernel/cpu/mce/inject.c

454

err = pci_read_config_dword(F3, NBCFG, &val);

arch/x86/kernel/cpu/mce/inject.c

457

__func__, PCI_FUNC(F3->devfn), NBCFG);

arch/x86/kernel/cpu/mce/inject.c

468

err = pci_write_config_dword(F3, NBCFG, val);

arch/x86/kernel/cpu/mce/inject.c

471

__func__, PCI_FUNC(F3->devfn), NBCFG);

crypto/cast5_generic.c

329

t = l; l = r; r = t ^ F3(r, Km[2], Kr[2]);

crypto/cast5_generic.c

332

t = l; l = r; r = t ^ F3(r, Km[5], Kr[5]);

crypto/cast5_generic.c

335

t = l; l = r; r = t ^ F3(r, Km[8], Kr[8]);

crypto/cast5_generic.c

338

t = l; l = r; r = t ^ F3(r, Km[11], Kr[11]);

crypto/cast5_generic.c

342

t = l; l = r; r = t ^ F3(r, Km[14], Kr[14]);

crypto/cast5_generic.c

373

t = l; l = r; r = t ^ F3(r, Km[14], Kr[14]);

crypto/cast5_generic.c

377

t = l; l = r; r = t ^ F3(r, Km[11], Kr[11]);

crypto/cast5_generic.c

380

t = l; l = r; r = t ^ F3(r, Km[8], Kr[8]);

crypto/cast5_generic.c

383

t = l; l = r; r = t ^ F3(r, Km[5], Kr[5]);

crypto/cast5_generic.c

386

t = l; l = r; r = t ^ F3(r, Km[2], Kr[2]);

crypto/cast6_generic.c

101

key[1] ^= F3(key[2], Tr[i % 4][5], Tm[i][5]);

crypto/cast6_generic.c

158

block[0] ^= F3(block[1], Kr[2], Km[2]);

crypto/cast6_generic.c

167

block[0] ^= F3(block[1], Kr[2], Km[2]);

crypto/cast6_generic.c

98

key[4] ^= F3(key[5], Tr[i % 4][2], Tm[i][2]);

crypto/rmd160.c

100

ROUND(dd, ee, aa, bb, cc, F3, K3, in[3], 11);

crypto/rmd160.c

101

ROUND(cc, dd, ee, aa, bb, F3, K3, in[10], 13);

crypto/rmd160.c

102

ROUND(bb, cc, dd, ee, aa, F3, K3, in[14], 6);

crypto/rmd160.c

103

ROUND(aa, bb, cc, dd, ee, F3, K3, in[4], 7);

crypto/rmd160.c

104

ROUND(ee, aa, bb, cc, dd, F3, K3, in[9], 14);

crypto/rmd160.c

105

ROUND(dd, ee, aa, bb, cc, F3, K3, in[15], 9);

crypto/rmd160.c

106

ROUND(cc, dd, ee, aa, bb, F3, K3, in[8], 13);

crypto/rmd160.c

107

ROUND(bb, cc, dd, ee, aa, F3, K3, in[1], 15);

crypto/rmd160.c

108

ROUND(aa, bb, cc, dd, ee, F3, K3, in[2], 14);

crypto/rmd160.c

109

ROUND(ee, aa, bb, cc, dd, F3, K3, in[7], 8);

crypto/rmd160.c

110

ROUND(dd, ee, aa, bb, cc, F3, K3, in[0], 13);

crypto/rmd160.c

111

ROUND(cc, dd, ee, aa, bb, F3, K3, in[6], 6);

crypto/rmd160.c

112

ROUND(bb, cc, dd, ee, aa, F3, K3, in[13], 5);

crypto/rmd160.c

113

ROUND(aa, bb, cc, dd, ee, F3, K3, in[11], 12);

crypto/rmd160.c

114

ROUND(ee, aa, bb, cc, dd, F3, K3, in[5], 7);

crypto/rmd160.c

115

ROUND(dd, ee, aa, bb, cc, F3, K3, in[12], 5);

crypto/rmd160.c

190

ROUND(ddd, eee, aaa, bbb, ccc, F3, KK3, in[15], 9);

crypto/rmd160.c

191

ROUND(ccc, ddd, eee, aaa, bbb, F3, KK3, in[5], 7);

crypto/rmd160.c

192

ROUND(bbb, ccc, ddd, eee, aaa, F3, KK3, in[1], 15);

crypto/rmd160.c

193

ROUND(aaa, bbb, ccc, ddd, eee, F3, KK3, in[3], 11);

crypto/rmd160.c

194

ROUND(eee, aaa, bbb, ccc, ddd, F3, KK3, in[7], 8);

crypto/rmd160.c

195

ROUND(ddd, eee, aaa, bbb, ccc, F3, KK3, in[14], 6);

crypto/rmd160.c

196

ROUND(ccc, ddd, eee, aaa, bbb, F3, KK3, in[6], 6);

crypto/rmd160.c

197

ROUND(bbb, ccc, ddd, eee, aaa, F3, KK3, in[9], 14);

crypto/rmd160.c

198

ROUND(aaa, bbb, ccc, ddd, eee, F3, KK3, in[11], 12);

crypto/rmd160.c

199

ROUND(eee, aaa, bbb, ccc, ddd, F3, KK3, in[8], 13);

crypto/rmd160.c

200

ROUND(ddd, eee, aaa, bbb, ccc, F3, KK3, in[12], 5);

crypto/rmd160.c

201

ROUND(ccc, ddd, eee, aaa, bbb, F3, KK3, in[2], 14);

crypto/rmd160.c

202

ROUND(bbb, ccc, ddd, eee, aaa, F3, KK3, in[10], 13);

crypto/rmd160.c

203

ROUND(aaa, bbb, ccc, ddd, eee, F3, KK3, in[0], 13);

crypto/rmd160.c

204

ROUND(eee, aaa, bbb, ccc, ddd, F3, KK3, in[4], 7);

crypto/rmd160.c

205

ROUND(ddd, eee, aaa, bbb, ccc, F3, KK3, in[13], 5);

drivers/edac/amd64_edac.c

1012

if (pvt->F3->device != PCI_DEVICE_ID_AMD_MI200_DF_F3)

drivers/edac/amd64_edac.c

223

pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);

drivers/edac/amd64_edac.c

265

amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);

drivers/edac/amd64_edac.c

267

amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);

drivers/edac/amd64_edac.c

2870

pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);

drivers/edac/amd64_edac.c

2877

pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);

drivers/edac/amd64_edac.c

2891

edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));

drivers/edac/amd64_edac.c

2903

amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);

drivers/edac/amd64_edac.c

2971

amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);

drivers/edac/amd64_edac.c

3001

amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);

drivers/edac/amd64_edac.c

3137

amd64_read_pci_cfg(pvt->F3, NBCFG, &val);

drivers/edac/amd64_edac.c

3276

struct pci_dev *F3)

drivers/edac/amd64_edac.c

3286

amd64_read_pci_cfg(F3, NBCTL, &value);

drivers/edac/amd64_edac.c

3292

amd64_write_pci_cfg(F3, NBCTL, value);

drivers/edac/amd64_edac.c

3294

amd64_read_pci_cfg(F3, NBCFG, &value);

drivers/edac/amd64_edac.c

3306

amd64_write_pci_cfg(F3, NBCFG, value);

drivers/edac/amd64_edac.c

3308

amd64_read_pci_cfg(F3, NBCFG, &value);

drivers/edac/amd64_edac.c

3328

struct pci_dev *F3)

drivers/edac/amd64_edac.c

3335

amd64_read_pci_cfg(F3, NBCTL, &value);

drivers/edac/amd64_edac.c

3339

amd64_write_pci_cfg(F3, NBCTL, value);

drivers/edac/amd64_edac.c

3343

amd64_read_pci_cfg(F3, NBCFG, &value);

drivers/edac/amd64_edac.c

3345

amd64_write_pci_cfg(F3, NBCFG, value);

drivers/edac/amd64_edac.c

3360

amd64_read_pci_cfg(pvt->F3, NBCFG, &value);

drivers/edac/amd64_edac.c

3443

mci->dev_name = pci_name(pvt->F3);

drivers/edac/amd64_edac.c

3465

mci->dev_name = pci_name(pvt->F3);

drivers/edac/amd64_edac.c

3615

mci->dev_name = pci_name(pvt->F3);

drivers/edac/amd64_edac.c

3856

if (pvt->F3->device == PCI_DEVICE_ID_AMD_MI200_DF_F3) {

drivers/edac/amd64_edac.c

3968

mci->pdev = &pvt->F3->dev;

drivers/edac/amd64_edac.c

3997

struct pci_dev *F3 = node_to_amd_nb(nid)->misc;

drivers/edac/amd64_edac.c

4014

pvt->F3 = F3;

drivers/edac/amd64_edac.c

4042

if (!enable_ecc_error_reporting(s, nid, F3))

drivers/edac/amd64_edac.c

4051

restore_ecc_error_reporting(s, nid, F3);

drivers/edac/amd64_edac.c

4077

struct pci_dev *F3 = node_to_amd_nb(nid)->misc;

drivers/edac/amd64_edac.c

4083

mci = edac_mc_del_mc(&F3->dev);

drivers/edac/amd64_edac.c

4089

restore_ecc_error_reporting(s, nid, F3);

drivers/edac/amd64_edac.c

729

amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);

drivers/edac/amd64_edac.c

734

amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);

drivers/edac/amd64_edac.c

762

amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);

drivers/edac/amd64_edac.c

773

amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);

drivers/edac/amd64_edac.c

777

amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);

drivers/edac/amd64_edac.h

329

struct pci_dev *F1, *F2, *F3;

drivers/gpu/drm/i915/intel_step.h

48

func(F3) \

drivers/gpu/drm/xe/xe_step_types.h

47

func(F3) \

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

2021

ASPEED_PINCTRL_PIN(F3),

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

680

SIG_EXPR_LIST_DECL_SINGLE(F3, SDA8, I2C8, I2C8_DESC);

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

681

PIN_DECL_1(F3, GPIOK7, SDA8);

drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c

683

FUNC_GROUP_DECL(I2C8, G5, F3);

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1339

SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1340

SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4);

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1341

PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4));

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

1342

FUNC_GROUP_DECL(ADC4, F3);

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

2019

ASPEED_PINCTRL_PIN(F3),

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

2572

ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8),

drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c

2573

ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8),

drivers/pinctrl/pinctrl-pic32.c

1385

PIC32_PINCTRL_GROUP(83, F3,

lib/crypto/md5.c

82

MD5STEP(F3, a, b, c, d, in[5] + 0xfffa3942, 4);

lib/crypto/md5.c

83

MD5STEP(F3, d, a, b, c, in[8] + 0x8771f681, 11);

lib/crypto/md5.c

84

MD5STEP(F3, c, d, a, b, in[11] + 0x6d9d6122, 16);

lib/crypto/md5.c

85

MD5STEP(F3, b, c, d, a, in[14] + 0xfde5380c, 23);

lib/crypto/md5.c

86

MD5STEP(F3, a, b, c, d, in[1] + 0xa4beea44, 4);

lib/crypto/md5.c

87

MD5STEP(F3, d, a, b, c, in[4] + 0x4bdecfa9, 11);

lib/crypto/md5.c

88

MD5STEP(F3, c, d, a, b, in[7] + 0xf6bb4b60, 16);

lib/crypto/md5.c

89

MD5STEP(F3, b, c, d, a, in[10] + 0xbebfbc70, 23);

lib/crypto/md5.c

90

MD5STEP(F3, a, b, c, d, in[13] + 0x289b7ec6, 4);

lib/crypto/md5.c

91

MD5STEP(F3, d, a, b, c, in[0] + 0xeaa127fa, 11);

lib/crypto/md5.c

92

MD5STEP(F3, c, d, a, b, in[3] + 0xd4ef3085, 16);

lib/crypto/md5.c

93

MD5STEP(F3, b, c, d, a, in[6] + 0x04881d05, 23);

lib/crypto/md5.c

94

MD5STEP(F3, a, b, c, d, in[9] + 0xd9d4d039, 4);

lib/crypto/md5.c

95

MD5STEP(F3, d, a, b, c, in[12] + 0xe6db99e5, 11);

lib/crypto/md5.c

96

MD5STEP(F3, c, d, a, b, in[15] + 0x1fa27cf8, 16);

lib/crypto/md5.c

97

MD5STEP(F3, b, c, d, a, in[2] + 0xc4ac5665, 23);