drivers/gpu/drm/radeon/evergreen.c

1384

if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))

drivers/gpu/drm/radeon/evergreen.c

1686

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/evergreen.c

1688

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/evergreen.c

1711

tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);

drivers/gpu/drm/radeon/evergreen.c

1713

WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);

drivers/gpu/drm/radeon/evergreen.c

2682

crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;

drivers/gpu/drm/radeon/evergreen.c

2695

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2700

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

drivers/gpu/drm/radeon/evergreen.c

2724

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2726

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

drivers/gpu/drm/radeon/evergreen.c

2830

tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);

drivers/gpu/drm/radeon/evergreen.c

2833

WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);

drivers/gpu/drm/radeon/evergreen.c

3808

if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {

drivers/gpu/drm/radeon/radeon_device.c

677

reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |

drivers/gpu/drm/radeon/radeon_device.c

678

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);

drivers/gpu/drm/radeon/radeon_device.c

680

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |

drivers/gpu/drm/radeon/radeon_device.c

681

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);

drivers/gpu/drm/radeon/radeon_device.c

684

reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |

drivers/gpu/drm/radeon/radeon_device.c

685

RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);