Symbol: EVERGREEN_CRTC0_REGISTER_OFFSET
drivers/gpu/drm/radeon/atombios_crtc.c
2198
radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
drivers/gpu/drm/radeon/cik.c
6881
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
drivers/gpu/drm/radeon/cik.c
6893
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
drivers/gpu/drm/radeon/cik.c
7233
WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
drivers/gpu/drm/radeon/cik.c
7245
WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET,
drivers/gpu/drm/radeon/cik.c
7298
EVERGREEN_CRTC0_REGISTER_OFFSET);
drivers/gpu/drm/radeon/cik.c
7315
WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
drivers/gpu/drm/radeon/cik.c
7321
WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
drivers/gpu/drm/radeon/cik.c
7323
WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
drivers/gpu/drm/radeon/evergreen.c
125
EVERGREEN_CRTC0_REGISTER_OFFSET,
drivers/gpu/drm/radeon/evergreen_cs.c
1032
EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,
drivers/gpu/drm/radeon/evergreen_cs.c
1040
EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
drivers/gpu/drm/radeon/radeon_device.c
677
reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
drivers/gpu/drm/radeon/radeon_display.c
1516
EVERGREEN_CRTC0_REGISTER_OFFSET,
drivers/gpu/drm/radeon/radeon_display.c
1840
EVERGREEN_CRTC0_REGISTER_OFFSET);
drivers/gpu/drm/radeon/radeon_display.c
1842
EVERGREEN_CRTC0_REGISTER_OFFSET);
drivers/gpu/drm/radeon/si.c
142
EVERGREEN_CRTC0_REGISTER_OFFSET,