EVENT_INDEX
EVENT_INDEX(0));
amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
EVENT_INDEX(4));
EVENT_INDEX(0));
EVENT_INDEX(5)));
EVENT_INDEX(5) |
EVENT_INDEX(5)));
ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
EVENT_INDEX(4));
EVENT_INDEX(0));
EVENT_INDEX(5)));
EVENT_INDEX(5) |
EVENT_INDEX(5)));
ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
EVENT_INDEX(5);
EVENT_INDEX(event_index));
EVENT_INDEX(5)));
EVENT_INDEX(5)));
EVENT_INDEX(5)));
EVENT_INDEX(5)));
radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
#define CCG_EVENT_MAX (EVENT_INDEX + 43)
return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX);