EP4
state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelAnalog;
state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBT;
state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDVBC;
state->m_Regs[EP4] = state->m_EP4 | state->m_IFLevelDigital;
state->m_Regs[EP4] |= 0x80;
state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 ????????? */
status = UpdateReg(state, EP4);
state->m_Regs[EP4] &= ~0x03; /* CAL_mode = 0 */
status = UpdateReg(state, EP4);
state->m_Regs[EP4] |= 0x03; /* CAL_Mode = 3 */
status = UpdateRegs(state, EP4, EP5);
state->m_Regs[EP4] &= ~0x03; /* CAL_Mode = 0 */
status = UpdateRegs(state, EP3, EP4);
state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x03) | 1; /* CAL_mode = 1 */
status = UpdateReg(state, EP4);
state->m_Regs[EP4] = (state->m_Regs[EP4] & ~0x1F); /* If level = 0, Cal mode = 0 */
status = UpdateRegs(state, EP3, EP4);
state->m_Regs[EP4] = 0x66;
state->m_Regs[EP4] = 0x64;
status = UpdateReg(state, EP4);
state->m_Regs[EP4] = state->m_EP4 | ((Standard > HF_AnalogMax) ? state->m_IFLevelDigital : state->m_IFLevelAnalog);