ENABLE_PCLK_PERIC1
ENABLE_PCLK_PERIC1,
GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1,
ENABLE_PCLK_PERIC1, 4, 0, 0),
ENABLE_PCLK_PERIC1, 5, 0, 0),
ENABLE_PCLK_PERIC1, 6, 0, 0),
ENABLE_PCLK_PERIC1, 7, 0, 0),
ENABLE_PCLK_PERIC1, 8, 0, 0),
ENABLE_PCLK_PERIC1, 9, 0, 0),
ENABLE_PCLK_PERIC1, 10, 0, 0),
ENABLE_PCLK_PERIC1, 11, 0, 0),
ENABLE_PCLK_PERIC1, 12, 0, 0),
ENABLE_PCLK_PERIC1, 13, 0, 0),
ENABLE_PCLK_PERIC1, 14, 0, 0),
ENABLE_PCLK_PERIC1, 15, 0, 0),
ENABLE_PCLK_PERIC1, 16, 0, 0),
ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_PERIC1, 18, 0, 0),
ENABLE_PCLK_PERIC1, 19, 0, 0),