ENABLE_PCLK_AUD
ENABLE_PCLK_AUD,
GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
ENABLE_PCLK_AUD, 10, 0, 0),
ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
ENABLE_PCLK_AUD, 6, 0, 0),
ENABLE_PCLK_AUD, 5, 0, 0),
ENABLE_PCLK_AUD, 4, 0, 0),
ENABLE_PCLK_AUD, 3, 0, 0),
GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
ENABLE_PCLK_AUD, 0, 0, 0),
ENABLE_PCLK_AUD,
GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),