drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

194

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v11_5_0.c

396

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

199

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_0.c

401

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

258

ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

545

ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

161

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

358

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

207

ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c

461

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

193

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

374

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

197

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

398

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

191

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.c

393

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

196

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c

386

tmp = REG_SET_FIELD(tmp, GCMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

627

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c

747

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

844

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c

981

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

144

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

403

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

162

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

387

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

201

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

219

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

487

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

495

tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB,

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

265

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

458

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

193

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c

388

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

218

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c

412

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

224

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

406

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

210

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.c

404

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

350

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v3_3.c

582

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

211

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_1_0.c

405

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

300

tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v4_2_0.c

563

ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

185

ENABLE_L1_TLB, 1);

drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c

455

ENABLE_L1_TLB, 0);

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.c

843

ENABLE_L1_TLB, 1,

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

425

HUBP_SF(HUBPREQ0_DCN_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, mask_sh),\

drivers/gpu/drm/amd/display/dc/hubp/dcn10/dcn10_hubp.h

626

type ENABLE_L1_TLB;\

drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c

77

ENABLE_L1_TLB, 1,

drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c

247

ENABLE_L1_TLB, 1,

drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c

64

ENABLE_L1_TLB, 1,

drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h

1082

type ENABLE_L1_TLB;\

drivers/gpu/drm/radeon/cik.c

5433

ENABLE_L1_TLB |

drivers/gpu/drm/radeon/evergreen.c

2422

tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |

drivers/gpu/drm/radeon/evergreen.c

2505

tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |

drivers/gpu/drm/radeon/ni.c

1262

ENABLE_L1_TLB |

drivers/gpu/drm/radeon/r600.c

1148

tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |

drivers/gpu/drm/radeon/r600.c

1240

tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |

drivers/gpu/drm/radeon/rv770.c

913

tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |

drivers/gpu/drm/radeon/rv770.c

990

tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |

drivers/gpu/drm/radeon/si.c

4279

ENABLE_L1_TLB |