drivers/gpu/drm/amd/amdgpu/cz_ih.c

65

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

drivers/gpu/drm/amd/amdgpu/cz_ih.c

85

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

65

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);

drivers/gpu/drm/amd/amdgpu/iceland_ih.c

85

ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

168

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

140

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

166

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/si_ih.c

41

ih_cntl |= ENABLE_INTR;

drivers/gpu/drm/amd/amdgpu/si_ih.c

54

ih_cntl &= ~ENABLE_INTR;

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

65

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

82

ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, ENABLE_INTR, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

110

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

146

tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));

drivers/gpu/drm/radeon/cik.c

6817

ih_cntl |= ENABLE_INTR;

drivers/gpu/drm/radeon/cik.c

6837

ih_cntl &= ~ENABLE_INTR;

drivers/gpu/drm/radeon/r600.c

3595

ih_cntl |= ENABLE_INTR;

drivers/gpu/drm/radeon/r600.c

3608

ih_cntl &= ~ENABLE_INTR;

drivers/gpu/drm/radeon/si.c

5905

ih_cntl |= ENABLE_INTR;

drivers/gpu/drm/radeon/si.c

5918

ih_cntl &= ~ENABLE_INTR;