drivers/acpi/cppc_acpi.c

1737

return cppc_set_reg_val(cpu, ENABLE, enable);

drivers/char/dsp56k.c

60

#define handshake(count, maxio, timeout, ENABLE, f) \

drivers/char/dsp56k.c

66

for (t = 0; t < timeout && !ENABLE; t++) \

drivers/char/dsp56k.c

68

if(!ENABLE) \

drivers/crypto/caam/dpseci.c

148

*en = dpseci_get_field(rsp_params->is_enabled, ENABLE);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c

156

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c

92

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c

406

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.c

392

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

377

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c

266

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c

289

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

417

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

2428

tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

248

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_0.c

252

ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

220

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

224

ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

220

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

224

ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

287

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

384

tmp = REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

246

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

250

ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

700

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

702

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

719

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

723

ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1127

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c

1212

doorbell = REG_SET_FIELD(doorbell, SDMA0_PAGE_DOORBELL, ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

516

doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

744

doorbell = REG_SET_FIELD(doorbell, SDMA_GFX_DOORBELL, ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c

850

doorbell = REG_SET_FIELD(doorbell, SDMA_PAGE_DOORBELL, ENABLE,

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

772

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

776

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

992

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

617

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

621

doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c

892

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

556

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

560

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

886

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

551

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

555

doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

905

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

533

doorbell = REG_SET_FIELD(doorbell, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

537

doorbell = REG_SET_FIELD(doorbell, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c

898

m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_SDMA_QUEUE0_DOORBELL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

450

reg = REG_SET_FIELD(reg, CKSVII2C_IC_ENABLE, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

472

if ((REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) &&

drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c

479

} else if (REG_GET_FIELD(reg_ic_enable, CKSVII2C_IC_ENABLE, ENABLE) == 0) {

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

150

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/tonga_ih.c

153

ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

191

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

195

ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

227

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

231

ENABLE, 0);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

291

val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

373

ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vega20_ih.c

375

WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);

drivers/gpu/drm/amd/amdgpu/vpe_v6_1.c

255

doorbell = REG_SET_FIELD(doorbell, VPEC_QUEUE0_DOORBELL, ENABLE, ring->use_doorbell ? 1 : 0);

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1347

unsigned char ENABLE : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1409

unsigned char ENABLE : 1;

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

1420

unsigned char ENABLE : 1;

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

116

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

117

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

118

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h

119

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

113

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

114

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

115

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h

116

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

80

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

81

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

82

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.h

83

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

103

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 0, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

104

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 1, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

105

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 2, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

106

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DTBCLK_DTO, ENABLE, 3, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

108

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 0, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

109

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 1, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

110

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 2, mask_sh),\

drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.h

111

DCCG_SFII(OTG, PIXEL_RATE_CNTL, DP_DTO, ENABLE, 3, mask_sh),\

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

779

ENABLE, enable);

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c

809

ENABLE, enable);

drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h

404

type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

138

if (psr_configuration.bits.ENABLE) {

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c

178

alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

1064

alpm_config.bits.ENABLE = link->replay_settings.config.alpm_mode != DC_ALPM_UNSUPPORTED ? 1 : 0;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

523

alpm_config.bits.ENABLE = (enable ? true : false);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

742

psr_configuration.bits.ENABLE = 1;

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

789

vtotal_control.bits.ENABLE = true;

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

556

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

drivers/gpu/drm/amd/display/dc/resource/dce100/dce100_resource.c

561

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

598

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c

603

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

674

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

drivers/gpu/drm/amd/display/dc/resource/dce60/dce60_resource.c

679

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

680

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT

drivers/gpu/drm/amd/display/dc/resource/dce80/dce80_resource.c

685

.ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

2950

smu->stb_context.enabled = REG_GET_FIELD(reg, MP1_PMI_3_START, ENABLE);

drivers/gpu/drm/bridge/imx/imx8mp-hdmi-pai.c

83

regmap_write(hdmi_pai->regmap, HTX_PAI_CTRL, ENABLE);

drivers/gpu/drm/bridge/parade-ps8640.c

378

ctrl == ENABLE ? "en" : "dis", ret);

drivers/gpu/drm/bridge/parade-ps8640.c

469

ps8640_bridge_vdo_control(ps_bridge, ENABLE);

drivers/gpu/drm/nouveau/dispnv50/base507c.c

128

NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/base507c.c

142

NVDEF(NV507C, SET_BASE_LUT_LO, ENABLE, USE_CORE_LUT));

drivers/gpu/drm/nouveau/dispnv50/base507c.c

82

NVDEF(NV507C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),

drivers/gpu/drm/nouveau/dispnv50/base827c.c

45

NVDEF(NV827C, SET_PROCESSING, USE_GAIN_OFS, ENABLE),

drivers/gpu/drm/nouveau/dispnv50/base907c.c

100

NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, USE_CORE_LUT));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

75

NVDEF(NV907C, SET_BASE_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

78

NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/base907c.c

94

NVVAL(NV907C, SET_BASE_LUT_LO, ENABLE, asyw->xlut.i.enable) |

drivers/gpu/drm/nouveau/dispnv50/core507d.c

46

NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/core507d.c

93

NVDEF(NV507D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/corec37d.c

64

NVDEF(NVC37D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

34

NVDEF(NVCA7D, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/coreca7d.c

38

NVDEF(NVCA7D, SET_NOTIFIER_CONTROL, NOTIFY, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/crc907d.c

36

NVDEF(NV907D, HEAD_SET_CRC_CONTROL, WIDE_PIPE_CRC, ENABLE);

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

33

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/crcca7d.c

36

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CRC, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/head.c

120

asyh->dither.enable = NVVAL_GET(mode, NV507D, HEAD_SET_DITHER_CONTROL, ENABLE);

drivers/gpu/drm/nouveau/dispnv50/head507d.c

133

NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

150

NVDEF(NV507D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

289

NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/head507d.c

304

NVDEF(NV507D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head507d.c

59

NVVAL(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

121

NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/head827d.c

138

NVDEF(NV827D, HEAD_SET_BASE_LUT_LO, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

40

NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/head827d.c

59

NVDEF(NV827D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

163

NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

182

NVDEF(NV907D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

257

NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/head907d.c

274

NVDEF(NV907D, HEAD_SET_OUTPUT_LUT_LO, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/head907d.c

88

NVVAL(NV907D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

drivers/gpu/drm/nouveau/dispnv50/head917d.c

41

NVVAL(NV917D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

drivers/gpu/drm/nouveau/dispnv50/head917d.c

89

NVDEF(NV917D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

115

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

133

NVDEF(NVC37D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/headc37d.c

96

NVVAL(NVC37D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

101

NVVAL(NVCA7D, HEAD_SET_DITHER_CONTROL, ENABLE, asyh->dither.enable) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

122

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, DISABLE) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

126

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

149

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_CURSOR, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

152

NVDEF(NVCA7D, HEAD_SET_CONTROL_CURSOR, ENABLE, ENABLE) |

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

181

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/headca7d.c

204

NVDEF(NVCA7D, HEAD_SET_SURFACE_ADDRESS_LO_OLUT, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

107

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

129

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ILUT, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

150

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

174

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_NOTIFIER, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

29

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, DISABLE));

drivers/gpu/drm/nouveau/dispnv50/wndwca7e.c

57

NVDEF(NVCA7E, SET_SURFACE_ADDRESS_LO_ISO, ENABLE, ENABLE));

drivers/gpu/drm/nouveau/nouveau_connector.h

71

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, DISABLE),

drivers/gpu/drm/nouveau/nouveau_connector.h

73

NVDEF(NV507D, HEAD_SET_DITHER_CONTROL, ENABLE, ENABLE),

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c

180

cp_set (ctx, XFER_SWITCH, ENABLE);

drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/disp.c

525

NVDEF(NV0073_CTRL_SPECIFIC, SET_OD_PACKET_TRANSMIT_CONTROL, ENABLE, YES) |

drivers/gpu/drm/xe/xe_guc_submit.c

1387

MAKE_SCHED_CONTEXT_ACTION(q, ENABLE);

drivers/input/keyboard/sun4i-lradc-keys.c

173

SAMPLE_RATE(0) | ENABLE(1), lradc->base + LRADC_CTRL);

drivers/input/serio/gscps2.c

315

gscps2_enable(ps2port, ENABLE);

drivers/media/pci/cobalt/cobalt-omnitek.c

102

iowrite32(ENABLE | SCATTER_GATHER_MODE | START, CS_REG(s->dma_channel));

drivers/net/ethernet/broadcom/sb1250-mac.c

1146

if (sc->rx_hw_checksum == ENABLE) {

drivers/net/ethernet/broadcom/sb1250-mac.c

1728

sc->rx_hw_checksum = ENABLE;

drivers/net/ethernet/broadcom/sb1250-mac.c

2245

if (sc->rx_hw_checksum == ENABLE)

drivers/net/ethernet/freescale/dpaa2/dpni.c

1024

dpni_set_field(cmd_params->enable, ENABLE, en);

drivers/net/ethernet/freescale/dpaa2/dpni.c

1060

*en = dpni_get_field(rsp_params->enabled, ENABLE);

drivers/net/ethernet/freescale/dpaa2/dpni.c

1087

dpni_set_field(cmd_params->enable, ENABLE, en);

drivers/net/ethernet/freescale/dpaa2/dpni.c

1123

*en = dpni_get_field(rsp_params->enabled, ENABLE);

drivers/net/ethernet/freescale/dpaa2/dpni.c

1255

dpni_set_field(cmd_params->en, ENABLE, en);

drivers/net/ethernet/freescale/dpaa2/dpni.c

1691

dpni_set_field(cmd_params->enable, ENABLE, taildrop->enable);

drivers/net/ethernet/freescale/dpaa2/dpni.c

1745

taildrop->enable = dpni_get_field(rsp_params->enable, ENABLE);

drivers/net/ethernet/freescale/dpaa2/dpni.c

268

*en = dpni_get_field(rsp_params->enabled, ENABLE);

drivers/net/ethernet/freescale/dpaa2/dpni.c

325

dpni_set_field(cmd_params->enable, ENABLE, en);

drivers/net/ethernet/freescale/dpaa2/dpni.c

368

*en = dpni_get_field(rsp_params->enabled, ENABLE);

drivers/net/ethernet/freescale/dpaa2/dpsw.c

176

dpsw_set_field(cmd_params->enable_state, ENABLE, en);

drivers/net/plip/plip.c

616

ENABLE(dev->irq);

drivers/net/plip/plip.c

694

ENABLE(dev->irq);

drivers/net/plip/plip.c

700

ENABLE(dev->irq);

drivers/net/plip/plip.c

800

ENABLE(dev->irq);

drivers/net/plip/plip.c

869

ENABLE(dev->irq);

drivers/net/plip/plip.c

907

ENABLE(dev->irq);

drivers/net/wireless/ti/wl1251/boot.c

50

wl1251_reg_write32(wl, ENABLE, 0x0);

drivers/net/wireless/ti/wl1251/reg.h

277

#define REG_ENABLE_TX_RX (ENABLE)

drivers/pci/hotplug/ibmphp_core.c

475

case ENABLE:

drivers/pci/hotplug/ibmphp_core.c

905

rc = validate(slot_cur, ENABLE);

drivers/pinctrl/pinctrl-palmas.c

323

FUNCTION_GROUP(enable, ENABLE)

drivers/scsi/aic7xxx/aic7770.c

236

ahc_outb(ahc, BCTL, ENABLE);

drivers/scsi/aic7xxx/aic7770.c

246

ahc_outb(ahc, BCTL, ENABLE);

drivers/scsi/isci/host.c

560

SMU_CQGR_GEN_BIT(ENABLE) |

drivers/scsi/isci/host.c

770

| (SMU_CQGR_GEN_BIT(ENABLE))

drivers/scsi/isci/phy.c

1192

enable_spinup_value &= ~SCU_ENSPINUP_GEN_BIT(ENABLE);

drivers/scsi/isci/phy.c

527

enable_spinup |= SCU_ENSPINUP_GEN_BIT(ENABLE);

drivers/scsi/isci/port.c

1447

pts_control_value |= SCU_PTSxCR_GEN_BIT(ENABLE) | SCU_PTSxCR_GEN_BIT(SUSPEND);

drivers/scsi/isci/port.c

1457

~(SCU_PTSxCR_GEN_BIT(ENABLE) | SCU_PTSxCR_GEN_BIT(SUSPEND));

drivers/scsi/isci/registers.h

561

(SCU_UFQGP_GEN_BIT(ENABLE) | value)

drivers/scsi/isci/registers.h

564

(~SCU_UFQGP_GEN_BIT(ENABLE) & value)

drivers/usb/gadget/udc/max3420_udc.c

332

if (todo == ENABLE) {

drivers/usb/gadget/udc/max3420_udc.c

936

ep->todo |= ENABLE;

drivers/video/fbdev/stifb.c

1011

int enable = (blank_mode == 0) ? ENABLE : DISABLE;

drivers/video/fbdev/stifb.c

1128

hyperResetPlanes(fb, ENABLE);

drivers/video/fbdev/stifb.c

771

case ENABLE:

sound/core/pcm.c

268

TSTAMP(ENABLE),