EN0_RXCR
outb_p(E8390_RXCONFIG | 0x58, e8390_base + EN0_RXCR);
outb_p(E8390_RXCONFIG | 0x48, e8390_base + EN0_RXCR);
outb_p(E8390_RXCONFIG | 0x40, e8390_base + EN0_RXCR);
outb_p(E8390_RXOFF|0x40, e8390_base + EN0_RXCR); /* 0x60 */
outb_p(E8390_RXCONFIG | 0x40, e8390_base + EN0_RXCR); /* rx on, */
{E8390_RXOFF|0x40, EN0_RXCR}, /* 0x60 Set to monitor */
ei_outb_p(E8390_RXOFF, e8390_base + EN0_RXCR); /* 0x20 */
ei_outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR); /* rx on, */
ei_outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR);
ei_outb_p(E8390_RXCONFIG | 0x18, e8390_base + EN0_RXCR);
ei_outb_p(E8390_RXCONFIG | 0x08, e8390_base + EN0_RXCR);
ei_outb_p(E8390_RXCONFIG, e8390_base + EN0_RXCR);
{E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */
{E8390_RXOFF, EN0_RXCR},
{E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */