EN0_ISR
while ((ei_inb(addr + EN0_ISR) & ENISR_RESET) == 0) {
ei_outb(ENISR_RESET, addr + EN0_ISR); /* Ack intr. */
ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
ei_outb(ENISR_RDC, nic_base + EN0_ISR);
while ((ei_inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) {
ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
ei_outb(ENISR_RDC, ioaddr + EN0_ISR); /* Ack intr. */
inb_p(e8390_base + EN0_ISR),
inb_p(e8390_base + EN0_ISR));
outb_p(0x00, e8390_base + EN0_ISR);
while ((interrupts = inb_p(e8390_base + EN0_ISR)) != 0 &&
outb_p(interrupts, e8390_base + EN0_ISR);
outb_p(interrupts, e8390_base + EN0_ISR);
if (!(inb(e8390_base + EN0_ISR) & interrupts))
outb_p(0, e8390_base + EN0_ISR);
outb_p(interrupts, e8390_base + EN0_ISR);
outb_p(ENISR_ALL, e8390_base + EN0_ISR); /* Ack. most intrs. */
outb_p(0xff, e8390_base + EN0_ISR); /* Ack. all intrs. */
unsigned char tx_completed = inb_p(e8390_base+EN0_ISR) & (ENISR_TX+ENISR_TX_ERR);
outb_p(0xFF, e8390_base + EN0_ISR);
outb_p(0xff, e8390_base + EN0_ISR);
{0xFF, EN0_ISR},
outb_p(0xFF, nic_base + EN0_ISR); /* Clear bogus intr. */
if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0)
outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */
if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) {
isr = inb(e8390_base+EN0_ISR);
writeb (ENISR_RDC, addr + EN0_ISR);
while ((readb (addr + EN0_ISR) & ENISR_RDC) == 0)
writeb (ENISR_RDC, addr + EN0_ISR);
writeb (ENISR_RDC, addr + EN0_ISR);
writeb (ENISR_RDC, addr + EN0_ISR);
ei_outb_p(0xFF, e8390_base + EN0_ISR);
ei_outb_p(0xff, e8390_base + EN0_ISR);
isr = ei_inb(e8390_base+EN0_ISR);
ei_inb_p(e8390_base + EN0_ISR),
ei_inb_p(e8390_base + EN0_ISR));
while ((interrupts = ei_inb_p(e8390_base + EN0_ISR)) != 0 &&
ei_outb_p(interrupts, e8390_base + EN0_ISR);
ei_outb_p(ENISR_COUNTERS, e8390_base + EN0_ISR); /* Ack intr. */
ei_outb_p(ENISR_RDC, e8390_base + EN0_ISR);
ei_outb_p(ENISR_ALL, e8390_base + EN0_ISR); /* Ack. most intrs. */
ei_outb_p(0xff, e8390_base + EN0_ISR); /* Ack. all intrs. */
ei_outb_p(ENISR_TX_ERR, e8390_base + EN0_ISR); /* Ack intr. */
ei_outb_p(ENISR_TX, e8390_base + EN0_ISR); /* Ack intr. */
ei_outb_p(ENISR_RX+ENISR_RX_ERR, e8390_base+EN0_ISR);
unsigned char tx_completed = ei_inb_p(e8390_base+EN0_ISR) & (ENISR_TX+ENISR_TX_ERR);
ei_outb_p(ENISR_OVER, e8390_base+EN0_ISR);
while ((inb_p(ioaddr + EN0_ISR) & ENISR_RESET) == 0)
outb_p(0xff, ioaddr + EN0_ISR); /* Ack all intr. */
{0xFF, EN0_ISR},
while ((inb_p(NE_BASE+EN0_ISR) & ENISR_RESET) == 0)
outb_p(ENISR_RESET, NE_BASE + EN0_ISR); /* Ack intr. */
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
outb_p(ENISR_RDC, nic_base + EN0_ISR);
while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0)
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
while ((inb(ioaddr + EN0_ISR) & ENISR_RESET) == 0)
outb(0xff, ioaddr + EN0_ISR);
{0xFF, EN0_ISR},
while ((inb(NE_BASE+EN0_ISR) & ENISR_RESET) == 0)
outb(ENISR_RESET, NE_BASE + EN0_ISR);
outb(ENISR_RDC, nic_base + EN0_ISR);
outb(ENISR_RDC, nic_base + EN0_ISR);
outb(ENISR_RDC, nic_base + EN0_ISR);
while ((inb(nic_base + EN0_ISR) & ENISR_RDC) == 0)
outb(ENISR_RDC, nic_base + EN0_ISR);
if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) {
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
outb_p(ENISR_RDC, nic_base + EN0_ISR);
while ((inb_p(nic_base + EN0_ISR) & ENISR_RDC) == 0)
outb_p(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */
{0xFF, EN0_ISR},
outb_p(0xFF, nic_base + EN0_ISR); /* Clear bogus intr. */
if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0)
outb_p(ENISR_RESET, nic_base + EN0_ISR); /* Ack intr. */
ei_outb(ENISR_RDC, nic_base + EN0_ISR);
while ((ei_inb(nic_base + EN0_ISR) & ENISR_RDC) == 0) {
ei_outb(ENISR_RDC, nic_base + EN0_ISR); /* Ack intr. */