EN0_IMR
outb_p(ENISR_ALL, e8390_base + EN0_IMR);
outb_p(ENISR_ALL, e8390_base + EN0_IMR);
inb_p(e8390_base + EN0_IMR));
outb_p(ENISR_ALL, e8390_base + EN0_IMR);
outb_p(0x00, e8390_base + EN0_IMR);
outb_p(ENISR_ALL, e8390_base + EN0_IMR);
{0x00, EN0_IMR}, /* Mask completion irq. */
outb_p(0x00, e8390_base + EN0_IMR);
ei_outb_p(0x00, e8390_base + EN0_IMR);
ei_outb_p(ENISR_ALL, e8390_base + EN0_IMR);
ei_outb_p(0x00, e8390_base + EN0_IMR);
ei_outb_p(ENISR_ALL, e8390_base + EN0_IMR);
ei_outb_p(ENISR_ALL, e8390_base + EN0_IMR);
ei_inb_p(e8390_base + EN0_IMR));
{0x00, EN0_IMR}, /* Mask completion irq. */
outb_p(0x50, ioaddr + EN0_IMR); /* Enable one interrupt. */
outb_p(0x00, ioaddr + EN0_IMR); /* Mask it again. */
{0x00, EN0_IMR},
{0x00, EN0_IMR}, /* Mask completion irq. */
outb(0x00, nic_addr+EN0_IMR); /* Disable all intrs. */
outb_p(0xff, nic_addr + EN0_IMR); /* Enable all interrupts. */
outb_p(0x00, nic_addr+EN0_IMR); /* Mask all intrs. again. */