EN0_DCFG
ei_outb(ax->plat->dcr_val & ~1, ioaddr + EN0_DCFG);
ei_outb(ax->plat->dcr_val, ei_local->mem + EN0_DCFG);
outb_p(endcfg, e8390_base + EN0_DCFG); /* 0x48 or 0x49 */
{0x01, EN0_DCFG}, /* Set word-wide access. */
ei_outb_p(endcfg, e8390_base + EN0_DCFG); /* 0x48 or 0x49 */
{0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
outb_p(DCR_VAL, ioaddr + EN0_DCFG);
{0x49, EN0_DCFG},
outb(0x49, ioaddr + EN0_DCFG);
{0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
outb_p(0x01, ioaddr + EN0_DCFG); /* Set word-wide access. */