EMIT2_off32
EMIT2_off32(add_2reg(0x84, BPF_REG_0, val_reg), add_2reg(0, ptr_reg, index_reg) /* SIB */, off);
EMIT2_off32(0x81, add_1reg(0xC8, dst_reg), user_vm_start >> 32);
EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
EMIT2_off32(0x69,
EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
EMIT2_off32(0xC7, 0x85, off);
EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
EMIT2_off32(0x0F, X86_JG + 0x10, 0);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), hi);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EAX), val);
EMIT2_off32(0x81, 0xEC, STACK_SIZE);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX),
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
EMIT2_off32(0xC7, add_1reg(0x80, IA32_EAX),
EMIT2_off32(0x8B,
EMIT2_off32(0xC7, add_1reg(0xC0, dst),
EMIT2_off32(0xC7, add_1reg(0xC0, sreg_lo), imm32);
EMIT2_off32(0xC7, add_1reg(0xC0, sreg_hi), hi);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_ECX), imm32);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EBX), hi);
EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
EMIT2_off32(0xC7, add_1reg(0xC0, IA32_EDX), val);