EMIT1
EMIT1(add_2mod(0x40, src_reg, dst_reg));
EMIT1(add_2mod(0x48, dst_reg, src_reg));
EMIT1(add_2mod(0x40, dst_reg, src_reg));
EMIT1(add_1mod(0x48, reg));
EMIT1(add_1mod(0x40, reg));
EMIT1(0x8B);
EMIT1(0x88);
EMIT1(0x89);
EMIT1(0xF0); /* lock prefix */
EMIT1(simple_alu_opcodes[atomic_op]);
EMIT1(0x87);
EMIT1(0xF0); /* lock prefix */
EMIT1(add_3mod(0x40, dst_reg, src_reg, index_reg));
EMIT1(add_3mod(0x48, dst_reg, src_reg, index_reg));
EMIT1(simple_alu_opcodes[atomic_op]);
EMIT1(0x87);
EMIT1(0x50); /* push rax */
EMIT1(0x51); /* push rcx */
EMIT1(0x59); /* pop rcx */
EMIT1(0x58); /* pop rax */
EMIT1(0x50); /* push rax */
EMIT1(0x52); /* push rdx */
EMIT1(0x99); /* cdq */
EMIT1(0x5A); /* pop rdx */
EMIT1(0x58); /* pop rax */
EMIT1(0x51); /* push rcx */
EMIT1(0x59); /* pop rcx */
EMIT1(0x66);
EMIT1(0x41);
EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
EMIT1(0x0F);
EMIT1(add_1reg(0xC8, dst_reg));
EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
EMIT1(0x45);
EMIT1(0xC6);
EMIT1(0xC7);
EMIT1(0xC9); /* leave */
EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
EMIT1(0x55); /* push rbp */
EMIT1(0x50); /* push rax */
EMIT1(0xC9); /* leave */
EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
EMIT1(0x53); /* push rbx */
EMIT1(add_1mod(0x48, BPF_REG_3)); /* cmp rdx,func */
EMIT1(0x5B); /* pop rbx */
EMIT1(x86_nops[noplen][i]);
EMIT1(0x90);
do { EMIT1(b1); EMIT4(b2, b3, b4, b5); } while (0)
EMIT1(0x50); /* push rax */
EMIT1(0x50); /* push rax */
do { EMIT1(b1); EMIT(off, 4); } while (0)
EMIT1(0x50); /* push rax */
EMIT1(0x50); /* push rax */
EMIT1(0x50); /* push rax */
EMIT1(0x55); /* push rbp */
EMIT1(0x41);
EMIT1(0xCC); /* int3 */
EMIT1(0xC3); /* ret */
EMIT1(0xCC); /* int3 */
EMIT1(0x58); /* pop rax */
EMIT1(0x58); /* pop rax */
EMIT1(0x58); /* pop rax */
EMIT1(0x58); /* pop rax */
EMIT1(add_2mod(0x40, dst_reg, dst_reg));
EMIT1(add_1mod(0x40, dst_reg));
EMIT1(add_2mod(0x40, dst_reg, src_reg));
EMIT1(0x55);
EMIT1(0x57);
EMIT1(0x56);
EMIT1(0x53);
EMIT1(0xC9); /* leave */
EMIT1(0xC3); /* ret */
EMIT1(0x51);
EMIT1(0x51);
EMIT1(0x51);
EMIT1(0x89);
EMIT1(add_2reg(0x80, IA32_EAX,
EMIT1(add_2reg(0xC0, dreg_lo, dreg_lo));
EMIT1(0x66);
EMIT1(add_2reg(0xC0, dreg_lo, dreg_lo));
EMIT1(0x0F);
EMIT1(add_1reg(0xC8, dreg_lo));
EMIT1(0x0F);
EMIT1(add_1reg(0xC8, dreg_lo));
EMIT1(0x0F);
EMIT1(add_1reg(0xC8, dreg_hi));
do { EMIT1(b1); EMIT(off, 4); } while (0)