arch/arm64/kvm/sys_regs.c

3821

EL2_REG_VNCR_GICv3(ICH_AP0R0_EL2),

arch/arm64/kvm/sys_regs.c

3822

EL2_REG_VNCR_GICv3(ICH_AP0R1_EL2),

arch/arm64/kvm/sys_regs.c

3823

EL2_REG_VNCR_GICv3(ICH_AP0R2_EL2),

arch/arm64/kvm/sys_regs.c

3824

EL2_REG_VNCR_GICv3(ICH_AP0R3_EL2),

arch/arm64/kvm/sys_regs.c

3825

EL2_REG_VNCR_GICv3(ICH_AP1R0_EL2),

arch/arm64/kvm/sys_regs.c

3826

EL2_REG_VNCR_GICv3(ICH_AP1R1_EL2),

arch/arm64/kvm/sys_regs.c

3827

EL2_REG_VNCR_GICv3(ICH_AP1R2_EL2),

arch/arm64/kvm/sys_regs.c

3828

EL2_REG_VNCR_GICv3(ICH_AP1R3_EL2),

arch/arm64/kvm/sys_regs.c

3832

EL2_REG_VNCR_GICv3(ICH_HCR_EL2),

arch/arm64/kvm/sys_regs.c

3837

EL2_REG_VNCR_GICv3(ICH_VMCR_EL2),

arch/arm64/kvm/sys_regs.c

3839

EL2_REG_VNCR_GICv3(ICH_LR0_EL2),

arch/arm64/kvm/sys_regs.c

3840

EL2_REG_VNCR_GICv3(ICH_LR1_EL2),

arch/arm64/kvm/sys_regs.c

3841

EL2_REG_VNCR_GICv3(ICH_LR2_EL2),

arch/arm64/kvm/sys_regs.c

3842

EL2_REG_VNCR_GICv3(ICH_LR3_EL2),

arch/arm64/kvm/sys_regs.c

3843

EL2_REG_VNCR_GICv3(ICH_LR4_EL2),

arch/arm64/kvm/sys_regs.c

3844

EL2_REG_VNCR_GICv3(ICH_LR5_EL2),

arch/arm64/kvm/sys_regs.c

3845

EL2_REG_VNCR_GICv3(ICH_LR6_EL2),

arch/arm64/kvm/sys_regs.c

3846

EL2_REG_VNCR_GICv3(ICH_LR7_EL2),

arch/arm64/kvm/sys_regs.c

3847

EL2_REG_VNCR_GICv3(ICH_LR8_EL2),

arch/arm64/kvm/sys_regs.c

3848

EL2_REG_VNCR_GICv3(ICH_LR9_EL2),

arch/arm64/kvm/sys_regs.c

3849

EL2_REG_VNCR_GICv3(ICH_LR10_EL2),

arch/arm64/kvm/sys_regs.c

3850

EL2_REG_VNCR_GICv3(ICH_LR11_EL2),

arch/arm64/kvm/sys_regs.c

3851

EL2_REG_VNCR_GICv3(ICH_LR12_EL2),

arch/arm64/kvm/sys_regs.c

3852

EL2_REG_VNCR_GICv3(ICH_LR13_EL2),

arch/arm64/kvm/sys_regs.c

3853

EL2_REG_VNCR_GICv3(ICH_LR14_EL2),

arch/arm64/kvm/sys_regs.c

3854

EL2_REG_VNCR_GICv3(ICH_LR15_EL2),