arch/arm64/kvm/sys_regs.c

3723

EL2_REG_VNCR_GICv3(ICH_AP0R0_EL2),

arch/arm64/kvm/sys_regs.c

3724

EL2_REG_VNCR_GICv3(ICH_AP0R1_EL2),

arch/arm64/kvm/sys_regs.c

3725

EL2_REG_VNCR_GICv3(ICH_AP0R2_EL2),

arch/arm64/kvm/sys_regs.c

3726

EL2_REG_VNCR_GICv3(ICH_AP0R3_EL2),

arch/arm64/kvm/sys_regs.c

3727

EL2_REG_VNCR_GICv3(ICH_AP1R0_EL2),

arch/arm64/kvm/sys_regs.c

3728

EL2_REG_VNCR_GICv3(ICH_AP1R1_EL2),

arch/arm64/kvm/sys_regs.c

3729

EL2_REG_VNCR_GICv3(ICH_AP1R2_EL2),

arch/arm64/kvm/sys_regs.c

3730

EL2_REG_VNCR_GICv3(ICH_AP1R3_EL2),

arch/arm64/kvm/sys_regs.c

3734

EL2_REG_VNCR_GICv3(ICH_HCR_EL2),

arch/arm64/kvm/sys_regs.c

3739

EL2_REG_VNCR_GICv3(ICH_VMCR_EL2),

arch/arm64/kvm/sys_regs.c

3741

EL2_REG_VNCR_GICv3(ICH_LR0_EL2),

arch/arm64/kvm/sys_regs.c

3742

EL2_REG_VNCR_GICv3(ICH_LR1_EL2),

arch/arm64/kvm/sys_regs.c

3743

EL2_REG_VNCR_GICv3(ICH_LR2_EL2),

arch/arm64/kvm/sys_regs.c

3744

EL2_REG_VNCR_GICv3(ICH_LR3_EL2),

arch/arm64/kvm/sys_regs.c

3745

EL2_REG_VNCR_GICv3(ICH_LR4_EL2),

arch/arm64/kvm/sys_regs.c

3746

EL2_REG_VNCR_GICv3(ICH_LR5_EL2),

arch/arm64/kvm/sys_regs.c

3747

EL2_REG_VNCR_GICv3(ICH_LR6_EL2),

arch/arm64/kvm/sys_regs.c

3748

EL2_REG_VNCR_GICv3(ICH_LR7_EL2),

arch/arm64/kvm/sys_regs.c

3749

EL2_REG_VNCR_GICv3(ICH_LR8_EL2),

arch/arm64/kvm/sys_regs.c

3750

EL2_REG_VNCR_GICv3(ICH_LR9_EL2),

arch/arm64/kvm/sys_regs.c

3751

EL2_REG_VNCR_GICv3(ICH_LR10_EL2),

arch/arm64/kvm/sys_regs.c

3752

EL2_REG_VNCR_GICv3(ICH_LR11_EL2),

arch/arm64/kvm/sys_regs.c

3753

EL2_REG_VNCR_GICv3(ICH_LR12_EL2),

arch/arm64/kvm/sys_regs.c

3754

EL2_REG_VNCR_GICv3(ICH_LR13_EL2),

arch/arm64/kvm/sys_regs.c

3755

EL2_REG_VNCR_GICv3(ICH_LR14_EL2),

arch/arm64/kvm/sys_regs.c

3756

EL2_REG_VNCR_GICv3(ICH_LR15_EL2),