EIR
intel_uncore_write(uncore, EIR, 0);
eir = intel_uncore_read(uncore, EIR);
gt->eir = intel_uncore_read(uncore, EIR);
*eir = intel_uncore_read(&dev_priv->uncore, EIR);
intel_uncore_write(&dev_priv->uncore, EIR, *eir);
*eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR);
#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
MMIO_D(EIR);
intflags = locked_regb_read(priv, EIR);
locked_reg_bfclr(priv, EIR, EIR_DMAIF);
locked_reg_bfclr(priv, EIR, EIR_TXIF);
locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF);
locked_reg_bfclr(priv, EIR, EIR_RXERIF);
nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
case EIR: /* Can be modified via single byte cmds */
encx24j600_clr_bits(priv, EIR, LINKIF);
encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
eir = encx24j600_read_reg(priv, EIR);
encx24j600_clr_bits(priv, EIR, RXABTIF);
encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
pr_info(DRV_NAME " EIR: %04X\n", encx24j600_read_reg(priv, EIR));
encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
if (encx24j600_read_reg(priv, EIR) & TXABTIF)
encx24j600_clr_bits(priv, EIR, TXIF);
i810_readb(EIR, mmio),