drivers/gpu/drm/i915/display/intel_psr.c

2298

psr_status_mask = EDP_PSR_STATUS_STATE_MASK;

drivers/gpu/drm/i915/display/intel_psr.c

3245

EDP_PSR_STATUS_STATE_MASK, 0, 200,

drivers/gpu/drm/i915/display/intel_psr.c

3252

EDP_PSR_STATUS_STATE_MASK,

drivers/gpu/drm/i915/display/intel_psr.c

3323

mask = EDP_PSR_STATUS_STATE_MASK;

drivers/gpu/drm/i915/display/intel_psr.c

4171

status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val);

drivers/gpu/drm/i915/display/intel_psr_regs.h

107

#define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0)

drivers/gpu/drm/i915/display/intel_psr_regs.h

108

#define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1)

drivers/gpu/drm/i915/display/intel_psr_regs.h

109

#define EDP_PSR_STATUS_STATE_SRDENT REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2)

drivers/gpu/drm/i915/display/intel_psr_regs.h

110

#define EDP_PSR_STATUS_STATE_BUFOFF REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3)

drivers/gpu/drm/i915/display/intel_psr_regs.h

111

#define EDP_PSR_STATUS_STATE_BUFON REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4)

drivers/gpu/drm/i915/display/intel_psr_regs.h

112

#define EDP_PSR_STATUS_STATE_AUXACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5)

drivers/gpu/drm/i915/display/intel_psr_regs.h

113

#define EDP_PSR_STATUS_STATE_SRDOFFACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6)