ECON1
locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
locked_reg_bfset(priv, ECON1,
locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
if (addr >= EIE && addr <= ECON1)
spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
poll_ready(priv, ECON1, ECON1_TXRTS, 0);
spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
case ECON1: /* Can be modified via single byte cmds */
pr_info(DRV_NAME " ECON1: %04X\n", encx24j600_read_reg(priv, ECON1));