Symbol: AFMT_VBI_PACKET_CONTROL
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
132
REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
87
REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
94
REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
98
REG_READ(AFMT_VBI_PACKET_CONTROL);
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c
99
REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
120
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
121
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
122
SE_SF(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
60
SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h
651
uint32_t AFMT_VBI_PACKET_CONTROL;
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.h
35
SRI(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_afmt.h
46
uint32_t AFMT_VBI_PACKET_CONTROL;
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.h
35
SRI(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
drivers/gpu/drm/amd/display/dc/dcn31/dcn31_afmt.h
46
uint32_t AFMT_VBI_PACKET_CONTROL;
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
80
REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
808
REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
815
REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
818
REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
87
REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.c
90
REG_UPDATE(AFMT_VBI_PACKET_CONTROL,
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
121
uint32_t AFMT_VBI_PACKET_CONTROL;
drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_stream_encoder.h
46
SRI(AFMT_VBI_PACKET_CONTROL, DIG, id), \
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
239
REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT,
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
243
REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
246
REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, 7);
drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c
258
REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, packet_index);
drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h
251
SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
70
SRI_ARR(AFMT_VBI_PACKET_CONTROL, AFMT, id), \