E10
SIG_EXPR_LIST_DECL_SINGLE(E10, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17));
SIG_EXPR_LIST_DECL_SINGLE(E10, RMII1RXER, RMII1, RMII1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(E10, RGMII1RXD3, RGMII1);
PIN_DECL_(E10, SIG_EXPR_LIST_PTR(E10, GPIOV1),
SIG_EXPR_LIST_PTR(E10, RMII1RXER),
SIG_EXPR_LIST_PTR(E10, RGMII1RXD3));
E10);
E10);
ASPEED_PINCTRL_PIN(E10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13),
SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31));
PIN_DECL_1(E10, GPIOR7, MDIO1);
FUNC_GROUP_DECL(MDIO1, D8, E10);
ASPEED_PINCTRL_PIN(E10),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17),
ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17),
PIN_GROUP(MDIO2, E10, E13);
PIN_GROUP(PE2SGRSTN, E10, PCIERC2_PERST);
PIN(E10),
[A26] = 71, [A14] = 72, [E10] = 73, [E13] = 74, [D12] = 75, [F10] = 76, [E11] = 77,