DW_REG
DW_REG(FIFO_PARTITION0);
DW_REG(FIFO_PARTITION1);
DW_REG(SAI_ERR);
DW_REG(GLOBAL_CFG);
DW_REG(SAR); /* Source Address Register */
DW_REG(DAR); /* Destination Address Register */
DW_REG(LLP); /* Linked List Pointer */
DW_REG(SSTAT);
DW_REG(DSTAT);
DW_REG(SSTATAR);
DW_REG(DSTATAR);
DW_REG(SGR);
DW_REG(DSR);
DW_REG(XFER);
DW_REG(BLOCK);
DW_REG(SRC_TRAN);
DW_REG(DST_TRAN);
DW_REG(ERROR);
DW_REG(STATUS_INT); /* r */
DW_REG(REQ_SRC);
DW_REG(REQ_DST);
DW_REG(SGL_REQ_SRC);
DW_REG(SGL_REQ_DST);
DW_REG(LAST_SRC);
DW_REG(LAST_DST);
DW_REG(CFG);
DW_REG(CH_EN);
DW_REG(ID);
DW_REG(TEST);
DW_REG(CLASS_PRIORITY0);
DW_REG(CLASS_PRIORITY1);
[DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4),
[DW_MIPI_CSI2RX_RESETN] = DW_REG(0x10),
[DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x14),
[DW_MIPI_CSI2RX_ERR1] = DW_REG(0x20),
[DW_MIPI_CSI2RX_ERR2] = DW_REG(0x24),
[DW_MIPI_CSI2RX_MSK1] = DW_REG(0x28),
[DW_MIPI_CSI2RX_MSK2] = DW_REG(0x2c),
[DW_MIPI_CSI2RX_CONTROL] = DW_REG(0x40),
[DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4),
[DW_MIPI_CSI2RX_RESETN] = DW_REG(0x8),
[DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40),
[DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44),
[DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48),
[DW_MIPI_CSI2RX_PHY_STOPSTATE] = DW_REG(0x4c),
[DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50),
[DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54),
[DW_MIPI_CSI2RX_IPI_MODE] = DW_REG(0x80),
[DW_MIPI_CSI2RX_IPI_VCID] = DW_REG(0x84),
[DW_MIPI_CSI2RX_IPI_DATATYPE] = DW_REG(0x88),
[DW_MIPI_CSI2RX_IPI_MEM_FLUSH] = DW_REG(0x8c),
[DW_MIPI_CSI2RX_IPI_SOFTRSTN] = DW_REG(0xa0),
[DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4),
[DW_MIPI_CSI2RX_RESETN] = DW_REG(0x8),
[DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40),
[DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44),
[DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48),
[DW_MIPI_CSI2RX_PHY_STOPSTATE] = DW_REG(0x4c),
[DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50),
[DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54),