drivers/gpu/drm/i915/gvt/handlers.c

2786

MMIO_DH(BXT_P_CR_GT_DISP_PWRON, D_BXT, NULL, bxt_gt_disp_pwron_write);

drivers/gpu/drm/i915/gvt/handlers.c

2787

MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY0), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2789

MMIO_DH(BXT_PHY_CTL_FAMILY(DPIO_PHY1), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2791

MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2793

MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2795

MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_C), D_BXT, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2798

MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH0), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2800

MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH0, 0), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2802

MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY0, DPIO_CH1), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2804

MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY0, DPIO_CH1, 0), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2806

MMIO_DH(BXT_PORT_PCS_DW12_GRP(DPIO_PHY1, DPIO_CH0), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2808

MMIO_DH(BXT_PORT_TX_DW3_LN(DPIO_PHY1, DPIO_CH0, 0), D_BXT,

drivers/gpu/drm/i915/gvt/handlers.c

2810

MMIO_DH(BXT_DE_PLL_ENABLE, D_BXT, NULL, bxt_de_pll_enable_write);

drivers/gpu/drm/i915/gvt/handlers.c

2811

MMIO_DFH(GEN8_L3SQCREG1, D_BXT, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2812

MMIO_DFH(GEN8_L3CNTLREG, D_BXT, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2813

MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2815

0, 0, D_BXT, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2817

0, 0, D_BXT, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2819

0, 0, D_BXT, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2821

0, 0, D_BXT, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2823

MMIO_DFH(GEN9_CTX_PREEMPT_REG, D_BXT, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2825

MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BXT, NULL, bxt_ppat_low_write);

drivers/gpu/drm/i915/gvt/handlers.c

93

return D_BXT;

drivers/gpu/drm/i915/gvt/mmio.h

50

#define D_GEN9PLUS (D_SKL | D_KBL | D_BXT | D_CFL)

drivers/gpu/drm/i915/gvt/mmio.h

51

#define D_GEN8PLUS (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)

drivers/gpu/drm/i915/gvt/mmio.h

53

#define D_SKL_PLUS (D_SKL | D_KBL | D_BXT | D_CFL)

drivers/gpu/drm/i915/gvt/mmio.h

54

#define D_BDW_PLUS (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)

drivers/gpu/drm/i915/gvt/mmio.h

57

#define D_ALL (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)