drivers/gpu/drm/i915/gvt/handlers.c

2403

MMIO_DH(FORCEWAKE_ACK_HSW, D_BDW, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2406

MMIO_DH(HSW_PWR_WELL_CTL1, D_BDW, NULL, power_well_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2407

MMIO_DH(HSW_PWR_WELL_CTL2, D_BDW, NULL, power_well_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2408

MMIO_DH(HSW_PWR_WELL_CTL3, D_BDW, NULL, power_well_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2409

MMIO_DH(HSW_PWR_WELL_CTL4, D_BDW, NULL, power_well_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2410

MMIO_DH(HSW_PWR_WELL_CTL5, D_BDW, NULL, power_well_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2411

MMIO_DH(HSW_PWR_WELL_CTL6, D_BDW, NULL, power_well_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2578

MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2579

MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2581

MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2582

MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2587

MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2589

MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2596

MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

87

return D_BDW;

drivers/gpu/drm/i915/gvt/mmio.h

51

#define D_GEN8PLUS (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)

drivers/gpu/drm/i915/gvt/mmio.h

54

#define D_BDW_PLUS (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)

drivers/gpu/drm/i915/gvt/mmio.h

56

#define D_PRE_SKL (D_BDW)

drivers/gpu/drm/i915/gvt/mmio.h

57

#define D_ALL (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)