drivers/gpu/drm/i915/gvt/cmd_parser.c

2047

{"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2049

{"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2052

{"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2056

D_ALL, 0, 1, cmd_handler_mi_wait_for_event},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2058

{"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2060

{"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2063

{"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2066

{"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2069

{"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2073

D_ALL, 0, 1, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2076

F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2079

{"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2082

{"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2086

D_ALL, 0, 1, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2088

{"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2091

{"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2095

R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2098

R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2100

{"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2103

D_ALL, 0, 8, NULL, CMD_LEN(0)},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2116

{"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2120

D_ALL, 0, 8, cmd_handler_lri},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2126

F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2129

{"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2132

{"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),

drivers/gpu/drm/i915/gvt/cmd_parser.c

2136

F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2140

F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2144

F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2148

F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2152

R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2154

{"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2164

F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2168

F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2172

R_RCS | R_BCS, D_ALL, 0, 2, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2174

{"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2177

{"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2181

F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2183

{"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2185

{"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2188

{"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2192

D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2194

{"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2197

{"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2200

{"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2203

{"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2207

D_ALL, ADDR_FIX_2(4, 5), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2209

{"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2212

D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2215

R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2219

F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2222

D_ALL, ADDR_FIX_1(4), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2225

F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2228

D_ALL, ADDR_FIX_1(4), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2231

D_ALL, ADDR_FIX_2(4, 7), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2234

F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2238

F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2240

{"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2244

F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2248

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2252

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2256

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2260

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2264

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2268

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2272

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2276

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2280

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2284

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2288

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2292

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2296

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2300

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2302

{"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2305

{"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2308

{"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2311

{"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2315

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2318

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2321

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2324

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2327

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2330

F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2333

F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2336

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2339

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2342

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2345

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2348

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2351

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2354

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2357

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2360

F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2363

F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2366

F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2369

F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2372

F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2408

R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2414

R_RCS, D_ALL, 0, 1, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2416

{"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2419

R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2422

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2424

{"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2426

{"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2428

{"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2437

D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2445

{"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2447

{"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2449

{"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2452

D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2454

{"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2456

{"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2459

R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2462

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2464

{"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2468

D_ALL, ADDR_FIX_1(2), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2471

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2474

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2477

D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2480

D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2483

D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2486

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2492

D_ALL, ADDR_FIX_1(2), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2495

R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2498

R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2501

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2504

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2507

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2510

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2513

F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2516

R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2519

D_ALL, 0, 9, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2538

{"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2541

{"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2543

{"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2546

{"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2549

{"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2554

{"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2558

F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2560

{"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2562

{"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2571

F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2573

{"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2576

{"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2579

{"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2582

{"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2584

{"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2587

{"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2590

{"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2593

{"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2596

{"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2600

F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2603

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2606

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2620

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2623

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2626

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2629

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2632

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2635

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2638

R_VCS, D_ALL, 0, 6, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2641

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2644

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2647

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2650

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2653

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2656

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2659

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2661

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2664

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2667

R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2670

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2673

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2676

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2679

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2682

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2685

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2688

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2691

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2694

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2697

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2700

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2702

{"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,

drivers/gpu/drm/i915/gvt/cmd_parser.c

2705

{"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2707

{"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2710

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2713

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2716

R_VCS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2718

{"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},

drivers/gpu/drm/i915/gvt/cmd_parser.c

2720

{"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,

drivers/gpu/drm/i915/gvt/handlers.c

2214

MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2217

MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);

drivers/gpu/drm/i915/gvt/handlers.c

2218

MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);

drivers/gpu/drm/i915/gvt/handlers.c

2219

MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);

drivers/gpu/drm/i915/gvt/handlers.c

2221

MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2227

MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2228

MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2229

MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2232

MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2236

MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2240

MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2244

MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2245

MMIO_GM_RDR(CCID(RENDER_RING_BASE), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2246

MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2248

MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2249

MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2250

MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2251

MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2252

MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2256

MMIO_RING_DFH(RING_REG, D_ALL,

drivers/gpu/drm/i915/gvt/handlers.c

2261

MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2263

MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2265

MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2267

MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2270

MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2271

MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2273

MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2274

MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2275

MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2277

MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2278

MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2279

MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2280

MMIO_DFH(FF_SLICE_CS_CHICKEN2, D_ALL,

drivers/gpu/drm/i915/gvt/handlers.c

2282

MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2283

MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2284

MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2286

MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS,

drivers/gpu/drm/i915/gvt/handlers.c

2288

MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2289

MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2290

MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2291

MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2292

MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2293

MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2294

MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2295

MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2296

MMIO_DFH(HSW_HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2297

MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2300

MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2302

MMIO_DH(TRANSCONF(display, TRANSCODER_B), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2304

MMIO_DH(TRANSCONF(display, TRANSCODER_C), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2306

MMIO_DH(TRANSCONF(display, TRANSCODER_EDP), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2308

MMIO_DH(DSPSURF(display, PIPE_A), D_ALL, NULL, pri_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2309

MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2311

MMIO_DH(DSPSURF(display, PIPE_B), D_ALL, NULL, pri_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2312

MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2314

MMIO_DH(DSPSURF(display, PIPE_C), D_ALL, NULL, pri_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2315

MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2317

MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2318

MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2320

MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2321

MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2323

MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2324

MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2327

MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,

drivers/gpu/drm/i915/gvt/handlers.c

2329

MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2340

MMIO_DH(_MMIO(_PCH_TRANSACONF), D_ALL, NULL, transconf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2341

MMIO_DH(_MMIO(_PCH_TRANSBCONF), D_ALL, NULL, transconf_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2343

MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2344

MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2345

MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2346

MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2347

MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2348

MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2349

MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2350

MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2351

MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);

drivers/gpu/drm/i915/gvt/handlers.c

2352

MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2353

MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2354

MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2355

MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2356

MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2357

MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2358

MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2360

MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,

drivers/gpu/drm/i915/gvt/handlers.c

2367

MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2368

MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2369

MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2370

MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2371

MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2373

MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2376

MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2377

MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2378

MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2379

MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2380

MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2382

MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2383

MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2384

MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2385

MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2386

MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2388

MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2389

MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2390

MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2391

MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2392

MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2394

MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_A), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2395

MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_B), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2396

MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_C), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2397

MMIO_DH(_MMIO(_TRANS_DDI_FUNC_CTL_EDP), D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2399

MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2400

MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2401

MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2404

MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2405

MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2413

MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2414

MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2415

MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2417

MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2418

MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2420

MMIO_DH(GEN6_MBCTL, D_ALL, NULL, mbctl_write);

drivers/gpu/drm/i915/gvt/handlers.c

2421

MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2423

MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);

drivers/gpu/drm/i915/gvt/handlers.c

2425

MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2426

MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2427

MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2428

MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2431

MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2432

MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2433

MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2437

MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2439

MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2440

MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2441

MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2442

MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2443

MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2444

MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2445

MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2446

MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2447

MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2448

MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2449

MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2457

MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2458

MMIO_RING_GM(RING_BBADDR, D_ALL, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2459

MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2460

MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2461

MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2462

MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2463

MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);

drivers/gpu/drm/i915/gvt/handlers.c

2471

MMIO_DH(GUC_STATUS, D_ALL, guc_status_read, NULL);