DSI_TIMING1
DUMPREG(DSI_TIMING1);
l = dsi_read_reg(dsi, DSI_TIMING1);
dsi_write_reg(dsi, DSI_TIMING1, l);
REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15);
r = dsi_read_reg(dsi, DSI_TIMING1);
dsi_write_reg(dsi, DSI_TIMING1, r);
if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) {
r = dsi_read_reg(dsi, DSI_TIMING1);
dsi_write_reg(dsi, DSI_TIMING1, r);
r = dsi_read_reg(dsi, DSI_TIMING1);
dsi_write_reg(dsi, DSI_TIMING1, r);
DUMPREG(DSI_TIMING1);
l = dsi_read_reg(dsidev, DSI_TIMING1);
dsi_write_reg(dsidev, DSI_TIMING1, l);
REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
r = dsi_read_reg(dsidev, DSI_TIMING1);
dsi_write_reg(dsidev, DSI_TIMING1, r);
if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
r = dsi_read_reg(dsidev, DSI_TIMING1);
dsi_write_reg(dsidev, DSI_TIMING1, r);
r = dsi_read_reg(dsidev, DSI_TIMING1);
dsi_write_reg(dsidev, DSI_TIMING1, r);