DSS_CONTROL
omap_hwmod_write(0x0, oh, DSS_CONTROL);
REG_FLD_MOD(dss, DSS_CONTROL, 0, 0, 0);
REG_FLD_MOD(dss, DSS_CONTROL, 1, 4, 4); /* venc dac demen */
REG_FLD_MOD(dss, DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
REG_FLD_MOD(dss, DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
DUMPREG(dss, DSS_CONTROL);
REG_FLD_MOD(dss, DSS_CONTROL, b, /* DISPC_CLK_SWITCH */
REG_FLD_MOD(dss, DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
REG_FLD_MOD(dss, DSS_CONTROL, 0, ctrl_bit, ctrl_bit);
REG_FLD_MOD(dss, DSS_CONTROL, 1, ctrl_bit, ctrl_bit);
REG_FLD_MOD(dss, DSS_CONTROL, l, 6, 6);
REG_FLD_MOD(dss, DSS_CONTROL, enable, 5, 5);
REG_FLD_MOD(dss, DSS_CONTROL, src, 15, 15);
REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 17);
REG_FLD_MOD(dss, DSS_CONTROL, val, 17, 16);
REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
DUMPREG(DSS_CONTROL);
REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */
REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */
REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */
REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
REG_FLD_MOD(DSS_CONTROL, src, 15, 15); /* VENC_HDMI_SWITCH */
return REG_GET(DSS_CONTROL, 15, 15);
REG_FLD_MOD(DSS_CONTROL, val, 17, 17);
REG_FLD_MOD(DSS_CONTROL, val, 17, 16);