DSR
DW_REG(DSR);
#define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
#define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
di_write_busy_wait(imxdi, DSR_CAF, DSR);
di_write_busy_wait(imxdi, DSR_NVF, DSR);
di_write_busy_wait(imxdi, DSR_TCO, DSR);
return di_handle_valid_state(imxdi, __raw_readl(imxdi->ioaddr + DSR));
DSR_MCO | DSR_TCO), DSR);
dsr = readl(imxdi->ioaddr + DSR);
di_write_busy_wait(imxdi, DSR_SVF, DSR);
dsr = readl(imxdi->ioaddr + DSR);
dsr = readl(imxdi->ioaddr + DSR);
writel(DSR_WEF, imxdi->ioaddr + DSR);
if ((readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
dsr = readl(imxdi->ioaddr + DSR);
alarm->pending = (readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
dsr = readl(imxdi->ioaddr + DSR);
di_write_wait(imxdi, DSR_CAF, DSR);
| (ctrl_dl->DSR ? TIOCM_DSR : 0)
unsigned int DSR:1;
unsigned int DSR:1;
if (old_ctrl.DSR != ctrl_dl.DSR)