DSI_VC_CTRL
DUMPREG(DSI_VC_CTRL(0));
DUMPREG(DSI_VC_CTRL(1));
DUMPREG(DSI_VC_CTRL(2));
DUMPREG(DSI_VC_CTRL(3));
return REG_GET(dsi, DSI_VC_CTRL(vc), 0, 0);
if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5) == 0)
if (REG_GET(dsi, DSI_VC_CTRL(vc), 5, 5)) {
REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 0, 0);
if (!wait_for_bit_change(dsi, DSI_VC_CTRL(vc), 0, enable)) {
r = dsi_read_reg(dsi, DSI_VC_CTRL(vc));
dsi_write_reg(dsi, DSI_VC_CTRL(vc), r);
if (REG_GET(dsi, DSI_VC_CTRL(vc), 9, 9) == enable)
REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), enable, 9, 9);
while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
while (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 6, 6); /* BTA_EN */
dsi_read_reg(dsi, DSI_VC_CTRL(vc));
if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(vc)), 16, 16)) {
if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20)) {
if (REG_GET(dsi, DSI_VC_CTRL(vc), 20, 20) == 0) {
REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 1, 4, 4);
REG_FLD_MOD(dsi, DSI_VC_CTRL(vc), 0, 4, 4);
REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 9, 9); /* LP */
REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_CMD), 0, 1, 1); /* SOURCE_L4 */
REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 9, 9); /* HS */
REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 1, 1); /* SOURCE_VP */
REG_FLD_MOD(dsi, DSI_VC_CTRL(VC_VIDEO), 1, 30, 30); /* DCS_CMD_ENABLE */
DUMPREG(DSI_VC_CTRL(0));
DUMPREG(DSI_VC_CTRL(1));
DUMPREG(DSI_VC_CTRL(2));
DUMPREG(DSI_VC_CTRL(3));
return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);