drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

300

dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN);

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

304

dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN | SHADOW_CLR);

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

308

dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN);

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

361

ret = regmap_update_bits(dsi->regmap, DSI_REG, UPDATE_PLL, UPDATE_PLL);

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

374

ret = regmap_update_bits(dsi->regmap, DSI_REG, UPDATE_PLL, 0);

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

401

dphy_pll_write(dsi, DSI_REG, val);

drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c

435

dphy_pll_write(dsi, DSI_REG, 0);

drivers/gpu/drm/omapdrm/dss/dsi.h

24

#define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)

drivers/gpu/drm/omapdrm/dss/dsi.h

25

#define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)

drivers/gpu/drm/omapdrm/dss/dsi.h

26

#define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)

drivers/gpu/drm/omapdrm/dss/dsi.h

27

#define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)

drivers/gpu/drm/omapdrm/dss/dsi.h

28

#define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)

drivers/gpu/drm/omapdrm/dss/dsi.h

29

#define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)

drivers/gpu/drm/omapdrm/dss/dsi.h

30

#define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)

drivers/gpu/drm/omapdrm/dss/dsi.h

31

#define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)

drivers/gpu/drm/omapdrm/dss/dsi.h

32

#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)

drivers/gpu/drm/omapdrm/dss/dsi.h

33

#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)

drivers/gpu/drm/omapdrm/dss/dsi.h

34

#define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)

drivers/gpu/drm/omapdrm/dss/dsi.h

35

#define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)

drivers/gpu/drm/omapdrm/dss/dsi.h

36

#define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)

drivers/gpu/drm/omapdrm/dss/dsi.h

37

#define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)

drivers/gpu/drm/omapdrm/dss/dsi.h

38

#define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)

drivers/gpu/drm/omapdrm/dss/dsi.h

39

#define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)

drivers/gpu/drm/omapdrm/dss/dsi.h

40

#define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)

drivers/gpu/drm/omapdrm/dss/dsi.h

41

#define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)

drivers/gpu/drm/omapdrm/dss/dsi.h

42

#define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)

drivers/gpu/drm/omapdrm/dss/dsi.h

43

#define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)

drivers/gpu/drm/omapdrm/dss/dsi.h

44

#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)

drivers/gpu/drm/omapdrm/dss/dsi.h

45

#define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)

drivers/gpu/drm/omapdrm/dss/dsi.h

46

#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)

drivers/gpu/drm/omapdrm/dss/dsi.h

47

#define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)

drivers/gpu/drm/omapdrm/dss/dsi.h

48

#define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)

drivers/gpu/drm/omapdrm/dss/dsi.h

49

#define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)

drivers/gpu/drm/omapdrm/dss/dsi.h

50

#define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)

drivers/gpu/drm/omapdrm/dss/dsi.h

51

#define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))

drivers/gpu/drm/omapdrm/dss/dsi.h

52

#define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))

drivers/gpu/drm/omapdrm/dss/dsi.h

53

#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))

drivers/gpu/drm/omapdrm/dss/dsi.h

54

#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))

drivers/gpu/drm/omapdrm/dss/dsi.h

55

#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))

drivers/gpu/drm/omapdrm/dss/dsi.h

56

#define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))

drivers/gpu/drm/omapdrm/dss/dsi.h

57

#define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))

drivers/gpu/drm/omapdrm/dss/dsi.h

65

#define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)

drivers/gpu/drm/omapdrm/dss/dsi.h

66

#define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)

drivers/gpu/drm/omapdrm/dss/dsi.h

67

#define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)

drivers/gpu/drm/omapdrm/dss/dsi.h

68

#define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)

drivers/gpu/drm/omapdrm/dss/dsi.h

69

#define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)

drivers/gpu/drm/omapdrm/dss/dsi.h

77

#define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)

drivers/gpu/drm/omapdrm/dss/dsi.h

78

#define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)

drivers/gpu/drm/omapdrm/dss/dsi.h

79

#define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)

drivers/gpu/drm/omapdrm/dss/dsi.h

80

#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)

drivers/gpu/drm/omapdrm/dss/dsi.h

81

#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

105

#define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

106

#define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

107

#define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

108

#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

109

#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

52

#define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

53

#define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

54

#define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

55

#define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

56

#define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

57

#define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

58

#define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

59

#define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

60

#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

61

#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

62

#define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

63

#define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

64

#define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

65

#define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

66

#define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

67

#define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

68

#define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

69

#define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

70

#define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

71

#define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

72

#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

73

#define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

74

#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

75

#define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

76

#define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

77

#define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

78

#define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

79

#define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

80

#define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

81

#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

82

#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

83

#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

84

#define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

85

#define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

93

#define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

94

#define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

95

#define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

96

#define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)

drivers/video/fbdev/omap2/omapfb/dss/dsi.c

97

#define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)