drivers/gpu/drm/vc4/vc4_dsi.c

1088

DSI_PORT_BIT(PHYC_CLANE_ENABLE) |

drivers/gpu/drm/vc4/vc4_dsi.c

1090

0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) |

drivers/gpu/drm/vc4/vc4_dsi.c

1125

~DSI_PORT_BIT(PHY_AFEC0_RESET));

drivers/gpu/drm/vc4/vc4_dsi.c

1294

DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));

drivers/gpu/drm/vc4/vc4_dsi.c

1337

DSI_PORT_BIT(CTRL_RESET_FIFOS));

drivers/gpu/drm/vc4/vc4_dsi.c

1340

DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED));

drivers/gpu/drm/vc4/vc4_dsi.c

1508

DSI_PORT_BIT(INT_ERR_SYNC_ESC), "LPDT sync");

drivers/gpu/drm/vc4/vc4_dsi.c

1510

DSI_PORT_BIT(INT_ERR_CONTROL), "data lane 0 sequence");

drivers/gpu/drm/vc4/vc4_dsi.c

1512

DSI_PORT_BIT(INT_ERR_CONT_LP0), "LP0 contention");

drivers/gpu/drm/vc4/vc4_dsi.c

1514

DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention");

drivers/gpu/drm/vc4/vc4_dsi.c

1516

DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout");

drivers/gpu/drm/vc4/vc4_dsi.c

1518

DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout");

drivers/gpu/drm/vc4/vc4_dsi.c

1520

DSI_PORT_BIT(INT_TA_TO), "turnaround timeout");

drivers/gpu/drm/vc4/vc4_dsi.c

1522

DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout");

drivers/gpu/drm/vc4/vc4_dsi.c

1526

DSI_PORT_BIT(INT_PHY_DIR_RTF))) {

drivers/gpu/drm/vc4/vc4_dsi.c

1529

} else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) {

drivers/gpu/drm/vc4/vc4_dsi.c

719

afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);

drivers/gpu/drm/vc4/vc4_dsi.c

721

afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);

drivers/gpu/drm/vc4/vc4_dsi.c

730

u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) |

drivers/gpu/drm/vc4/vc4_dsi.c

747

DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS));

drivers/gpu/drm/vc4/vc4_dsi.c

931

DSI_PORT_BIT(CTRL_RESET_FIFOS));