Symbol: DSC_NUM_BUF_RANGES
drivers/gpu/drm/display/drm_dsc_helper.c
1285
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
drivers/gpu/drm/display/drm_dsc_helper.c
237
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
drivers/gpu/drm/display/drm_dsc_helper.c
246
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
drivers/gpu/drm/display/drm_dsc_helper.c
314
DSC_NUM_BUF_RANGES - 1);
drivers/gpu/drm/display/drm_dsc_helper.c
340
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
drivers/gpu/drm/i915/display/intel_qp_tables.c
104
static const u8 rc_range_minqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
152
static const u8 rc_range_maxqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
200
static const u8 rc_range_minqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
248
static const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
296
static const u8 rc_range_minqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
314
static const u8 rc_range_maxqp420_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_8BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
332
static const u8 rc_range_minqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
352
static const u8 rc_range_maxqp420_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_10BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
38
static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
382
static const u8 rc_range_minqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
415
static const u8 rc_range_maxqp420_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP420_12BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_qp_tables.c
71
static const u8 rc_range_maxqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
drivers/gpu/drm/i915/display/intel_vdsc.c
166
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
drivers/gpu/drm/i915/display/intel_vdsc.c
214
for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
drivers/gpu/drm/i915/display/intel_vdsc.c
580
for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++)
drivers/gpu/drm/i915/display/intel_vdsc.c
630
for (i = 0; i < DSC_NUM_BUF_RANGES; i++)
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
137
for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
143
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
include/drm/display/drm_dsc.h
173
u16 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
include/drm/display/drm_dsc.h
179
struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];
include/drm/display/drm_dsc.h
499
u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1];
include/drm/display/drm_dsc.h
505
__be16 rc_range_parameters[DSC_NUM_BUF_RANGES];