DRMID
trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc);
trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en,
trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
trace_dpu_crtc_complete_flip(DRMID(crtc));
trace_dpu_crtc_vblank_cb(DRMID(crtc));
trace_dpu_crtc_frame_event_done(DRMID(crtc),
trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
trace_dpu_crtc_complete_commit(DRMID(crtc));
trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
DRMID(drm_enc), sw_event,
trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
DRMID(drm_enc), sw_event);
DRMID(drm_enc), sw_event, dpu_enc->rc_state);
trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
DRMID(drm_enc), sw_event, dpu_enc->rc_state);
DRMID(drm_enc), sw_event, dpu_enc->rc_state);
trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
DRM_ERROR("id:%u, unexpected sw_event: %d\n", DRMID(drm_enc),
trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
trace_dpu_enc_mode_set(DRMID(drm_enc));
trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay,
trace_dpu_enc_disable(DRMID(drm_enc));
trace_dpu_enc_underrun_cb(DRMID(drm_enc),
trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
trace_dpu_enc_frame_done_cb_not_busy(DRMID(drm_enc), event,
trace_dpu_enc_frame_done_cb(DRMID(drm_enc), i,
DRMID(drm_enc));
trace_dpu_enc_trigger_flush(DRMID(drm_enc),
DPU_DEBUG("encoder %d CWB enabled, skipping\n", DRMID(phys->parent));
trace_dpu_enc_trigger_start(DRMID(phys_enc->parent), ctl->idx);
DRM_DEBUG_KMS("id:%u ctl %d reset\n", DRMID(drm_enc),
trace_dpu_enc_prepare_kickoff(DRMID(drm_enc));
trace_dpu_enc_prepare_kickoff_reset(DRMID(drm_enc));
trace_dpu_enc_kickoff(DRMID(drm_enc));
DPU_DEBUG("[enc:%d] cdm_disable fmt:%p4cc\n", DRMID(phys_enc->parent),
DRMID(phys_enc->parent));
DRMID(phys_enc->parent), cdm_cfg->output_width,
DRMID(phys_enc->parent), ret);
DRMID(drm_enc), dpu_enc->frame_busy_mask[0]);
DRM_DEBUG_KMS("id:%u invalid timeout\n", DRMID(drm_enc));
trace_dpu_enc_frame_done_timeout(DRMID(drm_enc), event);
DRMID(phys_enc->parent),
DRMID(phys_enc->parent), func,
DRMID(phys_enc->parent), func);
DRMID(phys_enc->parent), func,
DRMID(phys_enc->parent),
DRMID(phys_enc->parent), func,
DRMID(phys_enc->parent), func,
trace_dpu_enc_irq_wait_success(DRMID(phys_enc->parent),
trace_dpu_enc_rc_enable(DRMID(drm_enc));
trace_dpu_enc_rc_disable(DRMID(drm_enc));
trace_dpu_enc_rc(DRMID(drm_enc), sw_event, dpu_enc->idle_pc_supported,
DRMID(drm_enc), sw_event);
DRMID(drm_enc), sw_event,
trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
DRMID(drm_enc), sw_event,
DRMID(drm_enc));
trace_dpu_enc_rc(DRMID(drm_enc), sw_event,
trace_dpu_enc_phys_cmd_pp_tx_done(DRMID(phys_enc->parent),
trace_dpu_enc_phys_cmd_pdone_timeout(DRMID(drm_enc),
DRMID(drm_enc),
DRM_DEBUG_KMS("id:%u pp:%d enable=%s/%d\n", DRMID(phys_enc->parent),
DRMID(phys_enc->parent),
trace_dpu_enc_phys_cmd_irq_enable(DRMID(phys_enc->parent),
trace_dpu_enc_phys_cmd_irq_disable(DRMID(phys_enc->parent),
trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable);
trace_dpu_enc_phys_cmd_connect_te(DRMID(phys_enc->parent), enable);
DRM_DEBUG_KMS("id:%u intf:%d state:%d\n", DRMID(phys_enc->parent),
DRM_DEBUG_KMS("id:%u pp:%d state:%d\n", DRMID(phys_enc->parent),
DRM_DEBUG_KMS("id:%u pp:%d pending_cnt:%d\n", DRMID(phys_enc->parent),
DRMID(phys_enc->parent), ret,
DRMID(phys_enc->parent),
DRMID(phys_enc->parent),
DRMID(phys_enc->parent), rc,
DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable,
DRMID(phys_enc->parent),
DRMID(phys_enc->parent),
DRMID(phys_enc->parent),
trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent),
trace_dpu_enc_phys_vid_irq_enable(DRMID(phys_enc->parent),
trace_dpu_enc_phys_vid_irq_disable(DRMID(phys_enc->parent),
trace_dpu_kms_commit(DRMID(crtc));
trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
trace_dpu_plane_disable(DRMID(plane), false,