DRAM_PHYS_BASE
region->region_base = DRAM_PHYS_BASE;
gaudi->hbm_bar_cur_addr = DRAM_PHYS_BASE;
if (gaudi_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
prop->dram_base_address = DRAM_PHYS_BASE;
inbound_region.addr = DRAM_PHYS_BASE;
#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE);
u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE);
if (hl_mem_area_inside_range(raw_addr, sizeof(raw_addr), DRAM_PHYS_BASE,
if (hl_mem_area_inside_range(scrambled_addr, sizeof(scrambled_addr), DRAM_PHYS_BASE,
prop->dram_base_address = DRAM_PHYS_BASE;
prop->dram_user_base_address = DRAM_PHYS_BASE + prop->dram_page_size;
prop->mmu_pgt_addr = DRAM_PHYS_BASE + hbm_drv_base_offset +
inbound_region.addr = DRAM_PHYS_BASE;
region->region_base = DRAM_PHYS_BASE;
gaudi2->dram_bar_cur_addr = DRAM_PHYS_BASE;
if (gaudi2_set_hbm_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);
if (goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE) == U64_MAX) {
goya_set_ddr_bar_base(hdev, DRAM_PHYS_BASE);
prop->dram_base_address = DRAM_PHYS_BASE;
inbound_region.addr = DRAM_PHYS_BASE;
region->region_base = DRAM_PHYS_BASE;
goya->ddr_bar_cur_addr = DRAM_PHYS_BASE;
#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
u32 dram_addr_lo = lower_32_bits(DRAM_PHYS_BASE);
u32 dram_addr_hi = upper_32_bits(DRAM_PHYS_BASE);