drivers/gpu/drm/amd/amdgpu/atombios_dp.c

203

static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

458

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/amd/amdgpu/atombios_dp.c

497

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

304

u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

331

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

394

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

549

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1035

u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1059

u8 after_cr[DP_LINK_STATUS_SIZE], u8 *req_volt,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1099

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

2097

u8 status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

496

u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

524

sizeof(hdr) + DP_LINK_STATUS_SIZE);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

537

DP_LINK_STATUS_SIZE);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

855

u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

899

void cdns_mhdp_set_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

912

void cdns_mhdp_set_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

925

u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

974

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/ite-it6505.c

1877

u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };

drivers/gpu/drm/bridge/ite-it6505.c

1950

u8 loop_count = 0, i, link_status[DP_LINK_STATUS_SIZE] = { 0 };

drivers/gpu/drm/bridge/ite-it6505.c

2250

u8 link_status[DP_LINK_STATUS_SIZE] = { 0 };

drivers/gpu/drm/bridge/ite-it6505.c

2431

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/synopsys/dw-dp.c

1602

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/synopsys/dw-dp.c

738

u8 status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/bridge/synopsys/dw-dp.c

781

u8 status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/synopsys/dw-dp.c

828

u8 status[DP_LINK_STATUS_SIZE], pattern;

drivers/gpu/drm/bridge/synopsys/dw-dp.c

960

u8 status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/bridge/tc358767.c

1094

u8 tmp[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/display/drm_dp_helper.c

112

bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

127

bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

135

u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

148

u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

162

u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

176

bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

196

bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

212

bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

221

bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

230

bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

77

static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)

drivers/gpu/drm/display/drm_dp_helper.c

810

u8 status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

813

DP_LINK_STATUS_SIZE);

drivers/gpu/drm/display/drm_dp_helper.c

82

static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/display/drm_dp_helper.c

832

u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/display/drm_dp_helper.c

840

DP_LINK_STATUS_SIZE);

drivers/gpu/drm/display/drm_dp_helper.c

845

DP_LINK_STATUS_SIZE - 1);

drivers/gpu/drm/display/drm_dp_helper.c

853

DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);

drivers/gpu/drm/display/drm_dp_helper.c

92

bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1234

DP_LINK_STATUS_SIZE);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1238

cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1245

cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1258

cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1302

cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/gma500/cdv_intel_dp.c

1314

cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)

drivers/gpu/drm/gma500/cdv_intel_dp.c

269

uint8_t link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

139

u8 lane_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

200

u8 lane_status[DP_LINK_STATUS_SIZE] = {0};

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

257

u8 lane_status[DP_LINK_STATUS_SIZE] = {0};

drivers/gpu/drm/i915/display/intel_dp.c

5680

u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/i915/display/intel_dp.c

5818

intel_dp_read_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/i915/display/intel_dp.c

5822

memset(link_status, 0, DP_LINK_STATUS_SIZE);

drivers/gpu/drm/i915/display/intel_dp.c

5826

link_status, DP_LINK_STATUS_SIZE - 2);

drivers/gpu/drm/i915/display/intel_dp.c

5844

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1059

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1126

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1538

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

1671

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/i915/display/intel_dp_link_training.c

395

const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/i915/display/intel_dp_link_training.c

415

const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/i915/display/intel_dp_link_training.c

451

const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/i915/display/intel_dp_link_training.c

489

const u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

919

const u8 old_link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/i915/display/intel_dp_link_training.c

920

const u8 new_link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

946

const u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/i915/display/intel_dp_link_training.c

963

u8 old_link_status[DP_LINK_STATUS_SIZE] = {};

drivers/gpu/drm/i915/display/intel_dp_link_training.c

965

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/i915/display/intel_dp_link_training.h

30

const u8 link_status[DP_LINK_STATUS_SIZE]);

drivers/gpu/drm/i915/display/intel_dp_link_training.h

46

const u8 link_status[DP_LINK_STATUS_SIZE]);

drivers/gpu/drm/i915/display/intel_dp_test.c

312

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/mediatek/mtk_dp.c

1626

u8 link_status[DP_LINK_STATUS_SIZE] = {};

drivers/gpu/drm/mediatek/mtk_dp.c

1697

u8 link_status[DP_LINK_STATUS_SIZE] = {};

drivers/gpu/drm/msm/dp/dp_ctrl.c

1426

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/msm/dp/dp_ctrl.c

1551

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/msm/dp/dp_ctrl.c

2240

const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/msm/dp/dp_ctrl.c

2260

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/msm/dp/dp_ctrl.c

2275

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/msm/dp/dp_link.c

48

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/msm/dp/dp_link.c

941

static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)

drivers/gpu/drm/nouveau/nouveau_dp.c

343

u8 stat[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/nouveau/nouveau_dp.c

452

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/radeon/atombios_dp.c

252

static void dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],

drivers/gpu/drm/radeon/atombios_dp.c

501

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/radeon/atombios_dp.c

542

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/rockchip/cdn-dp-core.c

531

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/rockchip/cdn-dp-core.c

539

DP_LINK_STATUS_SIZE)) {

drivers/gpu/drm/tegra/dp.c

483

u8 status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/tegra/dp.c

532

u8 status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/tegra/dp.c

582

u8 status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/tegra/dp.c

725

u8 status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/xlnx/zynqmp_dp.c

2336

u8 status[DP_LINK_STATUS_SIZE + 2];

drivers/gpu/drm/xlnx/zynqmp_dp.c

2344

DP_LINK_STATUS_SIZE + 2);

drivers/gpu/drm/xlnx/zynqmp_dp.c

693

u8 link_status[DP_LINK_STATUS_SIZE])

drivers/gpu/drm/xlnx/zynqmp_dp.c

761

u8 link_status[DP_LINK_STATUS_SIZE];

drivers/gpu/drm/xlnx/zynqmp_dp.c

827

u8 link_status[DP_LINK_STATUS_SIZE];

include/drm/display/drm_dp_helper.h

36

bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

include/drm/display/drm_dp_helper.h

38

bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],

include/drm/display/drm_dp_helper.h

40

bool drm_dp_post_lt_adj_req_in_progress(const u8 link_status[DP_LINK_STATUS_SIZE]);

include/drm/display/drm_dp_helper.h

41

u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],

include/drm/display/drm_dp_helper.h

43

u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],

include/drm/display/drm_dp_helper.h

45

u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],

include/drm/display/drm_dp_helper.h

62

bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],

include/drm/display/drm_dp_helper.h

64

bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],

include/drm/display/drm_dp_helper.h

66

bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);

include/drm/display/drm_dp_helper.h

67

bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);

include/drm/display/drm_dp_helper.h

68

bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);

include/drm/display/drm_dp_helper.h

698

u8 status[DP_LINK_STATUS_SIZE]);

include/drm/display/drm_dp_helper.h

702

u8 link_status[DP_LINK_STATUS_SIZE]);