drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

652

REG_SET(DP_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

666

REG_SET(DP_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

160

uint32_t DP_CONFIG;

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

54

SRI(DP_CONFIG, DP, id), \

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

88

SRI(DP_CONFIG, DP, id), \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.c

494

REG_SET(DP_CONFIG, 0,

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

47

SRI(DP_CONFIG, DP, id), \

drivers/gpu/drm/amd/display/dc/dio/dcn10/dcn10_link_encoder.h

90

uint32_t DP_CONFIG;

drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.h

36

SRI(DP_CONFIG, DP, id), \

drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.h

37

SRI(DP_CONFIG, DP, id), \

drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h

331

SRI_ARR(DP_CONFIG, DP, id), SRI_ARR(DP_DPHY_CNTL, DP, id), \

drivers/mtd/nand/ecc-mxic.c

178

reg = readl(mxic->regs + DP_CONFIG);

drivers/mtd/nand/ecc-mxic.c

180

writel(reg, mxic->regs + DP_CONFIG);

drivers/mtd/nand/ecc-mxic.c

187

reg = readl(mxic->regs + DP_CONFIG);

drivers/mtd/nand/ecc-mxic.c

189

writel(reg, mxic->regs + DP_CONFIG);

drivers/mtd/nand/ecc-mxic.c

298

writel(ECC_TYP(idx), mxic->regs + DP_CONFIG);