DP_TRAINING_PATTERN_2
case DP_TRAINING_PATTERN_2:
amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
DP_TRAINING_PATTERN_2);
DP_TRAINING_PATTERN_2);
case DP_TRAINING_PATTERN_2:
pattern = DP_TRAINING_PATTERN_2;
pattern = DP_TRAINING_PATTERN_2;
DP_TRAINING_PATTERN_2);
DP_TRAINING_PATTERN_2)) {
cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2);
ret = hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_2);
case DP_TRAINING_PATTERN_2:
case DP_TRAINING_PATTERN_2:
case DP_TRAINING_PATTERN_2:
case DP_TRAINING_PATTERN_2:
DP_TRAINING_PATTERN_2)) {
DP_PHY_DPRX, DP_TRAINING_PATTERN_2);
case DP_TRAINING_PATTERN_2:
return DP_TRAINING_PATTERN_2;
return DP_TRAINING_PATTERN_2;
DP_TRAINING_PATTERN_2) {
case DP_TRAINING_PATTERN_2:
mtk_dp->train_info.channel_eq_pattern = DP_TRAINING_PATTERN_2;
pattern = DP_TRAINING_PATTERN_2;
case DP_TRAINING_PATTERN_2:
case DP_TRAINING_PATTERN_2:
radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
case DP_TRAINING_PATTERN_2:
link->train.pattern = DP_TRAINING_PATTERN_2;
link->train.pattern = DP_TRAINING_PATTERN_2;
case DP_TRAINING_PATTERN_2:
pat = DP_TRAINING_PATTERN_2;