DP_TRAINING_PATTERN_1
case DP_TRAINING_PATTERN_1:
amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
DP_TRAINING_PATTERN_1);
DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE);
DP_TRAINING_PATTERN_1);
case DP_TRAINING_PATTERN_1:
ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
ret = dw_dp_link_train_set_pattern(dp, DP_TRAINING_PATTERN_1);
DP_TRAINING_PATTERN_1);
if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) {
cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1);
ret = hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_1);
case DP_TRAINING_PATTERN_1:
case DP_TRAINING_PATTERN_1:
case DP_TRAINING_PATTERN_1:
DP_PHY_DPRX, DP_TRAINING_PATTERN_1);
case DP_TRAINING_PATTERN_1:
DP_TRAINING_PATTERN_1)) {
case DP_TRAINING_PATTERN_1:
DP_TRAINING_PATTERN_1 |
if ((t & DP_TRAINING_PATTERN_MASK) == DP_TRAINING_PATTERN_1) {
aux_offset = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1;
msm_dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 |
case DP_TRAINING_PATTERN_1:
case DP_TRAINING_PATTERN_1:
radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
case DP_TRAINING_PATTERN_1:
link->train.pattern = DP_TRAINING_PATTERN_1;
link->train.pattern = DP_TRAINING_PATTERN_1;
case DP_TRAINING_PATTERN_1:
DP_TRAINING_PATTERN_1);
DP_TRAINING_PATTERN_1 |