drivers/gpu/drm/i915/display/intel_display_power_well.c

599

intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch),

drivers/gpu/drm/i915/display/intel_dp_aux.c

610

return DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

613

return DP_AUX_CH_CTL(AUX_CH_B);

drivers/gpu/drm/i915/display/intel_dp_aux.c

640

return DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

647

return DP_AUX_CH_CTL(AUX_CH_A);

drivers/gpu/drm/i915/display/intel_dp_aux.c

681

return DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

684

return DP_AUX_CH_CTL(AUX_CH_A);

drivers/gpu/drm/i915/display/intel_dp_aux.c

722

return DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

725

return DP_AUX_CH_CTL(AUX_CH_A);

drivers/gpu/drm/i915/gvt/handlers.c

1102

if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))

drivers/gpu/drm/i915/gvt/handlers.c

1105

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))

drivers/gpu/drm/i915/gvt/handlers.c

1108

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))

drivers/gpu/drm/i915/gvt/handlers.c

1111

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))

drivers/gpu/drm/i915/gvt/handlers.c

1205

offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {

drivers/gpu/drm/i915/gvt/handlers.c

1211

DP_AUX_CH_CTL(port_index))) {

drivers/gpu/drm/i915/gvt/handlers.c

2372

MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2621

MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2623

MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2625

MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

536

MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

931

MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

932

MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

933

MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4);