DP_TCL_NUM_RING_MAX
u32 desc_na[DP_TCL_NUM_RING_MAX];
struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
for (i = 0; i < DP_TCL_NUM_RING_MAX; i++)
for (i = 0; i < DP_TCL_NUM_RING_MAX; i++)
for (i = 0; i < DP_TCL_NUM_RING_MAX; i++)
u32 desc_na[DP_TCL_NUM_RING_MAX];
u32 tx_enqueued[DP_TCL_NUM_RING_MAX];
u32 tx_completed[DP_TCL_NUM_RING_MAX];
struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX];
struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX];
ath12k_hal_tcl_to_wbm_rbm_map_qcn9274[DP_TCL_NUM_RING_MAX] = {
ath12k_hal_tcl_to_wbm_rbm_map_qcn9274[DP_TCL_NUM_RING_MAX];
ath12k_hal_tcl_to_wbm_rbm_map_wcn7850[DP_TCL_NUM_RING_MAX] = {
ath12k_hal_tcl_to_wbm_rbm_map_wcn7850[DP_TCL_NUM_RING_MAX];