DP_SET_POWER_D0
amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
dpcd_power_state = DP_SET_POWER_D0;
if (irq_reg_rx_power_state != DP_SET_POWER_D0)
ret = drm_dp_dpcd_writeb(&dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
data = DP_SET_POWER_D0;
value |= DP_SET_POWER_D0;
DP_SET_POWER_D0);
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
if (mode != DP_SET_POWER_D0) {
mode == DP_SET_POWER_D0 ? "D0" : "D3");
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
[4] = DP_SET_POWER_D0,
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, DP_SET_POWER_D0);
value |= DP_SET_POWER_D0;
if ((pwr & DP_SET_POWER_MASK) != DP_SET_POWER_D0) {
pwr |= DP_SET_POWER_D0;
radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
DP_SET_POWER_D0);