Symbol: DPU_MAX_PLANES
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
195
for (i = 0; i < layout->num_planes && i < DPU_MAX_PLANES; ++i) {
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
249
for (i = 0; i < DPU_MAX_PLANES; i++)
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
321
uint32_t plane_addr[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
322
uint32_t plane_size[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
323
uint32_t plane_pitch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
33
#ifndef DPU_MAX_PLANES
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
388
for (color = 0; color < DPU_MAX_PLANES; color++) {
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
100
int init_phase_y[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
101
int phase_step_y[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
108
int num_ext_pxls_left[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
109
int num_ext_pxls_right[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
110
int num_ext_pxls_top[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
111
int num_ext_pxls_btm[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
117
int left_ftch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
118
int right_ftch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
119
int top_ftch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
120
int btm_ftch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
126
int left_rpt[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
127
int right_rpt[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
128
int top_rpt[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
129
int btm_rpt[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
131
uint32_t roi_w[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
132
uint32_t roi_h[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
138
enum dpu_hw_filter horz_filter[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
139
enum dpu_hw_filter vert_filter[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
98
int init_phase_x[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
99
int phase_step_x[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp_v13.c
168
for (color = 0; color < DPU_MAX_PLANES; color++) {
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
126
int32_t init_phase_x[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
127
int32_t phase_step_x[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
128
int32_t init_phase_y[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
129
int32_t phase_step_y[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
131
u32 preload_x[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
132
u32 preload_y[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
133
u32 src_width[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
134
u32 src_height[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
184
int32_t num_ext_pxls_lr[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
185
int32_t num_ext_pxls_tb[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
191
int32_t left_ftch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
192
int32_t right_ftch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
193
int32_t top_ftch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
194
int32_t btm_ftch[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
199
int32_t left_rpt[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
200
int32_t right_rpt[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
201
int32_t top_rpt[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
202
int32_t btm_rpt[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
288
int32_t init_phase_x[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
289
int32_t phase_step_x[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
290
int32_t init_phase_y[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
291
int32_t phase_step_y[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
293
uint32_t preload_x[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
294
uint32_t preload_y[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
295
uint32_t src_width[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
296
uint32_t src_height[DPU_MAX_PLANES];
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
462
for (i = 0; i < DPU_MAX_PLANES; i++) {
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
499
for (i = 0; i < DPU_MAX_PLANES; i++) {