drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c

544

aconnector->mst_mgr.dpcd[2] & DP_MAX_LANE_COUNT_MASK);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

1380

mhdp->link.num_lanes = dpcd[2] & DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/bridge/ite-it6505.c

1652

link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/display/drm_dp_helper.c

3213

return max_lanes & DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/display/drm_dp_helper.c

3270

data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

334

dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/i915/display/intel_dp_test.c

92

test_lane_count &= DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/msm/dp/dp_link.c

563

bp &= DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/nouveau/nouveau_dp.c

90

outp->dp.link_nr = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;

include/drm/display/drm_dp_helper.h

149

return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;