drivers/gpu/drm/amd/amdgpu/atombios_dp.c

743

if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1368

if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1383

DP_MAX_LANE_COUNT - DP_DPCD_REV];

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1894

if (dpcd_data[DP_MAX_LANE_COUNT - DP_DPCD_REV] == 0)

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c

1923

DP_MAX_LANE_COUNT - DP_DPCD_REV];

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

186

ret = drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

549

drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);

drivers/gpu/drm/bridge/ti-sn65dsi86.c

1024

ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1076

(intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {

drivers/gpu/drm/gma500/cdv_intel_dp.c

328

max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;

drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c

334

dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/nouveau/dispnv50/disp.c

1611

bool enhancedFraming = outp->dp.dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP;

drivers/gpu/drm/nouveau/nouveau_dp.c

327

if ( (outp->dp.dpcd[DP_MAX_LANE_COUNT] & 0x20) &&

drivers/gpu/drm/nouveau/nouveau_dp.c

90

outp->dp.link_nr = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;

drivers/gpu/drm/radeon/atombios_dp.c

826

if (drm_dp_dpcd_readb(&radeon_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)

drivers/gpu/drm/xlnx/zynqmp_dp.c

836

dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED)

include/drm/display/drm_dp_helper.h

149

return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;

include/drm/display/drm_dp_helper.h

156

(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);

include/drm/display/drm_dp_helper.h

163

(dpcd[DP_MAX_LANE_COUNT] & DP_POST_LT_ADJ_REQ_SUPPORTED);

include/drm/display/drm_dp_helper.h

177

dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;