drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c

365

DP_LANE_ALIGN_STATUS_UPDATED,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

477

retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

656

ret = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,

drivers/gpu/drm/display/drm_dp_helper.c

100

DP_LANE_ALIGN_STATUS_UPDATED);

drivers/gpu/drm/display/drm_dp_helper.c

129

u8 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);

drivers/gpu/drm/display/drm_dp_helper.c

182

lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);

drivers/gpu/drm/display/drm_dp_helper.c

214

u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);

drivers/gpu/drm/display/drm_dp_helper.c

223

u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);

drivers/gpu/drm/display/drm_dp_helper.c

232

u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1340

DP_LANE_ALIGN_STATUS_UPDATED);

drivers/gpu/drm/i915/gvt/handlers.c

1171

dpcd->data[DP_LANE_ALIGN_STATUS_UPDATED] |=

drivers/gpu/drm/msm/dp/dp_link.c

988

if (get_link_status(link->link_status, DP_LANE_ALIGN_STATUS_UPDATED) &