drivers/gpu/drm/i915/display/intel_display_power_well.c

554

intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch),

drivers/gpu/drm/i915/display/intel_dp_aux.c

598

return DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

601

return DP_AUX_CH_CTL(AUX_CH_B);

drivers/gpu/drm/i915/display/intel_dp_aux.c

628

return DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

635

return DP_AUX_CH_CTL(AUX_CH_A);

drivers/gpu/drm/i915/display/intel_dp_aux.c

669

return DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

672

return DP_AUX_CH_CTL(AUX_CH_A);

drivers/gpu/drm/i915/display/intel_dp_aux.c

710

return DP_AUX_CH_CTL(aux_ch);

drivers/gpu/drm/i915/display/intel_dp_aux.c

713

return DP_AUX_CH_CTL(AUX_CH_A);

drivers/gpu/drm/i915/gvt/handlers.c

1103

if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A)))

drivers/gpu/drm/i915/gvt/handlers.c

1106

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B)))

drivers/gpu/drm/i915/gvt/handlers.c

1109

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C)))

drivers/gpu/drm/i915/gvt/handlers.c

1112

reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D)))

drivers/gpu/drm/i915/gvt/handlers.c

1206

offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) {

drivers/gpu/drm/i915/gvt/handlers.c

1212

DP_AUX_CH_CTL(port_index))) {

drivers/gpu/drm/i915/gvt/handlers.c

2373

MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2622

MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2624

MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

drivers/gpu/drm/i915/gvt/handlers.c

2626

MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL,

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

530

MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

925

MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

926

MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4);

drivers/gpu/drm/i915/intel_gvt_mmio_table.c

927

MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4);