drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c

307

DP_ADJUST_REQUEST_LANE0_1,

drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c

667

lane01_adjust_address = DP_ADJUST_REQUEST_LANE0_1;

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

417

retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,

drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

472

retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

909

unsigned int idx = DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS + (lane >> 1);

drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c

922

unsigned int idx = DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS + (lane >> 1);

drivers/gpu/drm/display/drm_dp_helper.c

138

int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);

drivers/gpu/drm/display/drm_dp_helper.c

151

int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);

drivers/gpu/drm/display/drm_dp_helper.c

165

int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1248

int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);

drivers/gpu/drm/gma500/cdv_intel_dp.c

1261

int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);

drivers/gpu/drm/mediatek/mtk_dp.c

1641

drm_dp_dpcd_read(&mtk_dp->aux, DP_ADJUST_REQUEST_LANE0_1,

drivers/gpu/drm/mediatek/mtk_dp.c

1709

drm_dp_dpcd_read(&mtk_dp->aux, DP_ADJUST_REQUEST_LANE0_1,